Mark M. Budnik

A Power Delivery and Decoupling Network Minimizing Ohmic Loss and Supply Voltage Variation in Silicon Nanoscale Technologies

di/dt and IR events may cause large supply voltage variations and ohmic losses due to system parasitics. Today, decoupling capacitance is used to minimize the supply voltage variation, and parallelism in the power delivery path is used to reduce ohmic loss. Future integrated circuits, however, will exhibit large enough currents and current transients to mandate additional safeguards. A novel, distributed power delivery and decoupling network is introduced that reduces the supply voltage variation magnitude by more than 66% or the future ohmic loss by more than 27% (compared to todays power delivery and decoupling networks) using conventional processing and packaging techniques

A carbon nanotube capacitor structure

In this abstract, we present additional details on a new capacitor, CNCAP (carbon nanotube capacitor), compare it to existing integrated circuit capacitor technologies, and address its manufacturability. Properties of metallic, single wall CNTs (large surface area and relatively low resistance) allow for the creation of a very high density capacitor structure. In the CNCAP, each CNT electrode is surrounded by four CNTs connected to the opposing electrode. This structure allows for a potential capacitance/area greater than 100 fF/mum2. The electrical model of two parallel metallic, single wall, CNTs. The principle scattering mechanism in a CNT is due to acoustic phonons (under low bias) and the ideal CNT resistance is based on its length R = (h/4e2)(1+L/lambdaacc) where lambdaacc is the mean free path. The inductance, L, of the CNTs is taken as 4.07 nH/mum, which corresponds to the kinetic inductance. The quantum capacitance per unit length (CQ) of the CNTs is 388 aF/mum.

A carbon nanotube capacitor

We introduce a vertical carbon nanotube capacitor with high capacitance per unit area. Using an electrical model of single-walled, metallic carbon nanotubes and the extracted capacitance values of a carbon nanotube bundle network, we develop an electrical model for the capacitor. The device can exhibit a capacitance greater than 175fF/µm2.

Electrical models for vertical carbon nanotube capacitors

We present electrical models for a carbon nanotube capacitor with high capacitance per unit area. We begin by introducing the concept of using vertically grown carbon nanotubes to develop a carbon nanotube capacitor. Three potential structures of the carbon nanotube capacitor are presented. We determine the capacitance per unit area for each structure. The carbon nanotube capacitor structures exhibit capacitances per unit area from 50fF/µm2 to 387fF/µm2 as a function of carbon nanotube diameter, inter-nanotube spacing, and nanotube length.

Carbon Nanotube Capacitors

Capacitors are important components in many integrated circuits. They serve numerous roles in analog and mixed signal circuits, including switched capacitor filters and sampleand-hold circuits. In addition, capacitors provide a vital role in the decoupling of microprocessors, digital signal processors, and microcontrollers from power supply variations. Traditional integrated circuit capacitors use a parallel plate structure. The capacitance of these parallel plate structures is fundamentally limited by the die area they consume and the thickness of the dielectric material between the parallel plates. However, increasing the capacitance of traditional parallel plate capacitors by increasing the die area (resulting in a more expensive component) or decreasing the dielectric thickness (resulting in a higher leakage current) contradicts two of the fundamental tenements of integrated circuit design (ITRS, 2008). Carbon nanotubes (CNTs) are nanotechnology materials that have been in prominence for the last several years. They are cylinders of graphene that can exhibit radii on the order of nanometers. CNTs exhibit a number of properties that make them attractive as potential horizontal and vertical interconnects in future integrated circuits (Naeemi et al., 2004, Naeemi et al., 2005, Raychowdhury & Roy, 2004). The same properties allow CNTs to be used to create a new capacitor structure suitable for use in future integrated circuits (Budnik et al., 2006). In this chapter we introduce these CNT capacitor structures and compare their capacitance per unit area with existing technologies. The chapter is organized as follows. Section 2 reviews the structure and limitations of traditional parallel plate capacitors in integrated circuits. Section 3 briefly introduces CNTs, their varieties, and how they can be manufactured. Section 4 reviews the electrical models that have been developed for CNTs for use in the development of a CNT capacitor model. Section 5 formally introduces CNT capacitor devices as an extrapolation of the currently proposed CNT interconnects. Three different CNT capacitor structures and their electrical models are presented in this section. Finally, the conclusions are presented in Section 6.

Introduction to Nanotechnology: implementation of a cooperative program for gifted and talented elementary school children

Around the world, primary and secondary schools are challenged to implement appropriate programs for their gifted and talented students. In this paper, we present how our communitys public school system and our college of engineering collaboratively developed and implemented a program on Nanotechnology for a group of forty 9–11 year olds on a completely self-sustaining basis. The programs objectives and outcomes are aligned with our states Core Science and Academic Standards. Modest student fees (US

A Thin, Vertical, Parallel Plate Capacitor with Multi-Wall Carbon Nanotube Electrodes

30 per child) cover the training and salary for undergraduate students to serve as instructors, as well as the salary for the K-12 teachers/mentors to be present as additional support during the sessions. After completing the program, the children met over 90% of the objectives. Subjectively, the program was highly regarded by both parents and students. Survey results from children who attended the program and their parents were 5.00/5.00 and 4.79/5.00, respectively.

Implications of SiO/sub 2/ Breakdown in an Integrated Nanoscale Power Supply

We propose a new capacitor structure which uses carbon nanotube electrodes and is suitable for use in advanced integrated circuit technologies. Metallic carbon nanotubes have characteristics which make them well suited for capacitor electrodes (low resistance and large surface area per unit volume). We demonstrate that our thin vertical plate carbon nanotube capacitor can exhibit a capacitance per unit area of 175 fF/mum2.

Welcome to IEDEC 2014

Future nanoscale microprocessors may have integrated voltage regulators providing multiple supply voltages to meet their power and performance requirements. For their high input voltage, we have developed a model predicting the rate of dielectric breakdown of such regulators. Input parameters include oxide thickness, temperature, operating current, input voltage, Weibull slope, and the total charge passing through the dielectric when 63% of the samples will fail. For a 100A power supply, the predicted time to 100PPM failures (at 2.0V, 425K, and with a 1.5nm thick silicon dioxide gate) is slightly more than ten years.

Welcome to ISQED 2010

On behalf of the IEDEC Organizing Committee we would like to welcome you to the 4th Interdisciplinary Engineering Design & Education Conference (IEDEC 2014).