Mark Muir

The Reconfigurable Instruction Cell Array

This paper presents a novel instruction cell-based reconfigurable computing architecture for low-power applications, thereafter referred to as the reconfigurable instruction cell array (RICA). For the development of the RICA, a top-down software driven approach was taken and revealed as one of the key design decisions for a flexible, easy to program, low-power architecture. These features make RICA an architecture that inherently solves the main design requirements of modern low-power devices. Results show that it delivers considerably less power consumption when compared to leading VLIW and low-power digital signal processors, but still maintaining their throughput performance.

Mapping Real Time Operating System on Reconfigurable Instruction Cell Based Architectures

This paper presents the porting of an RTOS Micro C/OS-II on a novel reconfigurable instruction cell based architecture which fills the gap between DSP, FPGA and ASIC with high performance, high flexibility and ANSI-C support. WiMAX physical layer program has been implemented on the target architecture with the RTOS support. A semaphore based synchronization scheme is used to improve the task independence. The research lays a foundation for further exploration of multithreading on multiple target architectures.

Multi-core Architectures with Dynamically Reconfigurable Array Processors for the WiMAX Physical Layer

Wireless internet access technologies have significant market potential, especially the WiMAX protocol which can offer data rate of tens of Mbps. A significant demand for embedded high performance WiMAX solutions is forcing designers to seek single-chip multiprocessor or multi-core systems that offer competitive advantages in terms of all performance metrics, such as speed, power and area. Through the provision of a degree of flexibility similar to that of a DSP and performance and power consumption advantages approaching that of an ASIC, emerging dynamically reconfigurable processors are proving to be strong candidates for future high performance multi-core processor systems. This paper presents several new single-chip multi-core architectures, based on newly emerging dynamically reconfigurable processor cores, for the WiMAX physical layer. A simulation platform is proposed in order to explore and implement various multi-core solutions combining different memory architectures and task partitioning schemes. The paper describes the architectures, the simulation environment, and demonstrates that up to 4.2x speedup can be achieved by employing four dynamically reconfigurable processor cores with individual local memory units.

Multicore Architectures With Dynamically Reconfigurable Array Processors for Wireless Broadband Technologies

Wireless Internet-access technologies have significant market potential, particularly the Worldwide Interoperability for Microwave Access (WiMAX) protocol which can offer data rates of tens of megabits per second. A significant demand for embedded high-performance WiMAX solutions is forcing designers to seek single-chip multicore systems that offer competitive advantages in terms of all performance metrics, such as speed, power, and area. Through the provision of a degree of flexibility similar to that of a DSP and performance and power consumption advantages approaching that of an application-specific integrated circuit, emerging dynamically reconfigurable (DR) processors are proving to be strong candidates for processing cores in future high-performance multicore-processor systems. This paper presents several new single-chip multicore architectures for the WiMAX application based on recently emerging coarse-grained DR processor cores. A simulation platform is proposed in order to explore and implement various multicore solutions combining different memory architectures and task-partitioning schemes. This paper describes the different architectures, the simulation environment, and several task-partitioning methods and demonstrates that up to 7.3 and 12 times speedup can be achieved by employing eight and ten DR processor cores for both the WiMAX transmitter and receiver sections, respectively. A comparison with other WiMAX multicore solutions is given in order to demonstrate that our best solution delivers a high throughput at relatively low area cost.

MRPSIM: A TLM based simulation tool for MPSOCS targeting dynamically reconfigurable processors

As multiprocessor system-on-chip (MPSoC) approaches become popular in embedded system designs, simulation tools for modelling these systems are highly in demand for evaluating the performance and cost at both hardware design stage and software development phase. This paper presents a fast, flexible, and cycle-accurate simulation tool for MPSoCs targeting emerging dynamically reconfigurable processors. Based on a complex embedded application - WiMAX, a range of test benches have been implemented on the proposed simulation tool for evaluating the impact on simulation speed of a variety of architectural parameters and task mapping strategies. Experimental results demonstrate that up to 60K cycles per second can be achieved.

Efficient Implementation of Wireless Applications on Multi-core Platforms Based on Dynamically Reconfigurable Processors

Wireless internet access technologies such as WiMAX have significant market potential. The high demand for embedded high performance WiMAX solutions is forcing designers to seek multi-core systems which offer competitive advantages in terms of all performance metrics. By providing the flexibility of a DSP with performance and power consumption approaching that of an ASIC, emerging dynamically reconfigurable processors are proving to be stronger candidates than conventional general-purpose processors or DSPs for future multi-core systems. This paper presents several multi-core solutions, based on newly emerging dynamically reconfigurable processor cores targeting WiMAX based applications. Coming with a SystemC trace-driven multi-core simulator, a simulation platform has been proposed in order to explore and implement various multi-core solutions combining different task partitioning strategies and inter-process communication methods.

H.264/AVC In-Loop De-Blocking Filter Targeting a Dynamically Reconfigurable Instruction Cell Based Architecture

We present a new de-blocking filter module fully optimised for use on a recently introduced dynamically reconfigurable, instruction cell based architecture. The module consists of a novel combination of standard software transforms alongside architecture specific techniques and aims to reduce reconfiguration overheads and increase utilisation of resources. Our proposed filter outperforms the standard FFMpeg based filter code on the target architecture by 4.5 times.

A Multi Objective GA Based Physical Placement Algorithm for Heterogeneous Dynamically Reconfigurable Arrays

This paper presents the preliminary results of a physical placement algorithm for heterogeneous Dynamically Reconfigurable Arrays (DRA), based on a multi-objective, multi-threaded GA. The algorithm deals with the spatial and temporal nature of the configurations used in DRAs, in an attempt to find a suitable layout for a wide range of applications, since general applicability is a key criteria for DRAs.

A Multi-object GA Based Physical Placement Algorithm for Heterogeneous Dynamicaly Reconfigurable Arrays

This paper presents a physical placement algorithm, for Dynamically Reconfigurable Arrays (DRA), based on a multi-objective, multi-threaded GA implementation. The algorithm deals with the spatial and temporal nature of the configurations used in DRAs, in an attempt to find a suitable layout for a wide range of applications, since general applicability is a key criteria for DRAs. The results show that the proposed algorithm significantly improves the routability and total wire-length of the mapped configuration sets, with results ranging from 21% to 55% for various quality metrics.

A dynamically reconfigurable asynchronous processor

The main design requirements for high-throughput mobile applications are energy efficiency and programmability. This paper presents a novel dynamically reconfigurable processor that targets these requirements. Our processor consists of a heterogeneous array of coarse grain asynchronous cells. The architecture maintains most of the benefits of custom asynchronous design, while also providing programmability via conventional high-level languages. Results show that our processor delivers considerably lower power consumption when compared to a market leading VLIW and a low-power ARM processor, while maintaining their throughput performance. For example, our processor resulted in a reduction in power consumption over the ARM7 processor of over 9 times when running the bilinear demosaicing algorithm at the same throughput. Our processor was also compared to an equivalent synchronous design, resulting in a power reduction of up to 15%.