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Dive into the research topics where Mark Neidengard is active.

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Featured researches published by Mark Neidengard.


IEEE Journal of Solid-state Circuits | 2009

Next Generation Intel¯ Core™ Micro-Architecture (Nehalem) Clocking

Nasser A. Kurd; Praveen Mosalikanti; Mark Neidengard; Jonathan P. Douglas; Rajesh Kumar

This paper describes the core and I/O clocking architecture of the next generation Intelreg Coretrade micro-architecture processor (Nehalem), designed on a 45 nm process technology. Local PLL placement provides modularity and power-efficient scalability by allowing independent frequency and voltage domains. Fast-locking, low-skew PLLs are used to achieve 56% lock time reduction and 30% long-tem jitter improvement. Adaptive frequency, supply, and duty cycle mechanisms combine for up to 5% core frequency gain at iso-voltage. Jitter attenuating DLLs with enhanced linearity and plusmn15% duty cycle correction drive a differential, low-swing I/O receiver clock distribution, reducing jitter by 25% and enabling 25.6 GB/s Intelreg QuickPath Interconnect bandwidth and three-channel DDR3 traffic up to 32 GB/s.


IEEE Journal of Solid-state Circuits | 2015

Haswell: A Family of IA 22 nm Processors

Nasser A. Kurd; Muntaquim Chowdhury; Edward A. Burton; Thomas P. Thomas; Christopher P. Mozak; Brent R. Boswell; Praveen Mosalikanti; Mark Neidengard; Anant Deval; Ashish Khanna; Nasirul Chowdhury; Ravi Rajwar; Timothy M. Wilson; Rajesh Kumar

We describe the 4th Generation Intel® Core™ processor family (codenamed “Haswell”) implemented on Intel® 22 nm technology and intended to support form factors from desktops to fan-less Ultrabooks™. Performance enhancements include a 102 GB/sec L4 eDRAM cache, hardware support for transactional synchronization, and new FMA instructions that double FP operations per clock. Power improvements include Fully-Integrated Voltage Regulators ( ~ 50% battery life extension), new low-power states (95% standby power savings), optimized MCP I/O system (1.0-1.22 pJ/b), and improved DDR I/O circuits (40% active and 100x idle power savings). Other improvements include full-platform optimization via integrated display I/O interfaces.


IEEE Journal of Solid-state Circuits | 2011

A Family of 32 nm IA Processors

Nasser A. Kurd; Subramani Bhamidipati; Christopher P. Mozak; Jeffrey L. Miller; Praveen Mosalikanti; Timothy M. Wilson; Ali M. El-Husseini; Mark Neidengard; Ramy E. Aly; Mahadev Nemani; Muntaquim Chowdhury; Rajesh Kumar

Westmere is the latest IA processor family for mobile, desktop and server market segments, implemented on Intels second-generation high-k metal gate 32 nm process. Westmere not only increases core count, cache size, and frequency within the previous generations power envelope, it also provides further improvements in power efficiency, feature set, and support for combo DDR3 and low voltage DDR3 despite using a thin gate technology.


Archive | 2011

FREQUENCY SYNTHESIS METHODS AND SYSTEMS

Nasser A. Kurd; Robert J. Greiner; Mark Neidengard; Vaughn J. Grossnickle


Archive | 2011

APPARATUS, SYSTEM, AND METHOD FOR RE-SYNTHESIZING A CLOCK SIGNAL

Mark Neidengard; Vaughn J. Grossnickle; Nasser A. Kurd; Jeffrey L. Krieger


Archive | 2009

EDGE-TIMING ADJUSTMENT CIRCUIT

Mark Neidengard


Archive | 2008

Oscillating divider topology

Mark Neidengard


Archive | 2006

Missing clock pulse detector

Mark Neidengard


IEEE Transactions on Circuits and Systems I-regular Papers | 2018

A Flexible, Low-Power Analog PLL for SoC and Processors in 14nm CMOS

Kuan-Yueh James Shen; Syed Feruz Syed Farooq; Yongping Fan; Khoa Minh Nguyen; Qi Wang; Mark Neidengard; Nasser A. Kurd; Amr Elshazly


Archive | 2017

BIDIRECTIONAL GRAY CODE COUNTER

Mark Neidengard

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