Jonathan P. Douglas

FIVR — Fully integrated voltage regulators on 4th generation Intel® Core™ SoCs

Intels® 4th generation Core™ microprocessors are powered by Fully Integrated Voltage Regulators (FIVR). These 140 MHz multi-phase buck regulators are integrated into the 22nm processor die, and feature up to 80 MHz unity gain bandwidth, non-magnetic package trace inductors and on-die MIM capacitors. FIVRs are highly configurable, allowing them to power a wide range of products from 3W fanless tablets to 300W servers. FIVR helps enable 50% or more battery life improvements for mobile products and more than doubles the peak power available for burst workloads.

Next generation Intel® micro-architecture (Nehalem) clocking architecture

This paper describes the next generation Intelreg micro-architecture (Nehalem) 45 nm IA processorpsilas core and I/O clocking architecture. Among the highlights are: configurable clocking, fastlock low-skew PLLs, high reference clock frequencies, analog supply tracking system, adaptive frequency clocking, low jitter Intelreg QuickPath interconnect and Intelreg QuickPath memory controller clock generation, and jitter-attenuating DLLs.

Next Generation Intel¯ Core™ Micro-Architecture (Nehalem) Clocking

This paper describes the core and I/O clocking architecture of the next generation Intelreg Coretrade micro-architecture processor (Nehalem), designed on a 45 nm process technology. Local PLL placement provides modularity and power-efficient scalability by allowing independent frequency and voltage domains. Fast-locking, low-skew PLLs are used to achieve 56% lock time reduction and 30% long-tem jitter improvement. Adaptive frequency, supply, and duty cycle mechanisms combine for up to 5% core frequency gain at iso-voltage. Jitter attenuating DLLs with enhanced linearity and plusmn15% duty cycle correction drive a differential, low-swing I/O receiver clock distribution, reducing jitter by 25% and enabling 25.6 GB/s Intelreg QuickPath Interconnect bandwidth and three-channel DDR3 traffic up to 32 GB/s.

5.9 Haswell: A family of IA 22nm processors

The 4th Generation Intel® Core™ processor, codenamed Haswell, is a family of products implemented on Intel 22nm Tri-gate process technology [1]. The primary goals for the Haswell program are platform integration and low power to enable smaller form factors. Haswell incorporates several building blocks, including: platform controller hubs (PCHs), memory, CPU, graphics and media processing engines, thus creating a portfolio of product segments from fan-less Ultrabooks™ to high-performance desktop, as shown in Fig. 5.9.1. It also integrates a number of new technologies: a fully integrated voltage regulator (VR) consolidating 5 platform VRs down to 1, on-die eDRAM cache for improved graphics performance, lower-power states, optimized IO interfaces, an Intel AVX2 instruction set that supports floating-point multiply-add (FMA), and 256b SIMD integer achieving 2× the number of floating-point and integer operations over its predecessor. The 22nm process is optimized for Haswell and includes 11 metal layers (2 additional metal layers vs. Ivy Bridge [2]), high-density metal-insulator-metal (MIM) capacitors, and is tuned for different leakage/speed targets based on the market segment. For example, in some low-power products, the process is optimized to reduce leakage by 75% at Vmin, while paying only 12% intrinsic device degradation at the high-voltage corner.

Designing a 3 GHz, 130 nm, Intel/sup /spl reg// Pentium/sup /spl reg// 4 processor

The design of an IA32 processor fabricated in a state-of-the art 130 nm CMOS process with improved six layers of dual-damascene copper metallization is described. This paper describes the methodology employed to simultaneously achieve high frequency and low power in the Pentium/sup /spl reg// 4 processor, suitable for all segments-server, desktop, and mobile-meeting diverse challenges of performance, power delivery, and dissipation.

Broadwell: A family of IA 14nm processors

Intel Core™ M and 5th generation of Core™ processors (code named Broadwell) are fabricated on an optimized 14 nm process technology node resulting in a 49% reduction in feature-neutral die area. 14nm created a new optimized process flavor for Core™ M to improve energy efficiency for mobile devices. Techniques and optimizations were implemented to deliver 2.5x TDP reduction coupled with up-to 60% higher graphics performance. New process technology combined with various design techniques reduced the minimum voltage of operation by 50 m V. Broadwell introduces the second generation of Fully Integrated Voltage Regulator with better droop control and parallel boot LVR along with other power-reduction features resulting in 35% reduction in active and standby power over first generation. 3DL inductor technology introduced for the first time in Broadwell, enables 30 % reduction in package thickness and improved low-load efficiency. IO re-partitioning of the SOC and a major re-design of DDR system resulted in 30% reduction in I/O power. Shutting down various parts of the SOC die in various idle states (C* states) resulted in 60% reduction in the idle power. New software controlled co-optimization methods were implemented such as duty-cycle control and dynamic display support to improve the energy efficiency of the graphics and the display subsystem.

Scalable, sub-1W, sub-10ps clock skew, global clock distribution architecture for Intel ® Core ™ i7/i5/i3 microprocessors

This paper describes global clock distribution architecture of Intel^® Core^™ i7/i5/i3 microprocessor family. Highlight of this paper is a pseudo-recombinant clock distribution architecture successfully implemented in 32nm/45nm generation of Core^™ i7/i5/i3 processors. This clock distribution topology achieves less than 10ps clock skew while consuming a maximum power of 1 Watt across entire operating voltage and frequency range.