Marko Magerl

Broadband characterization of SMA connectors by measurements

This paper presents the characterization of various types of SubMiniature version A (SMA) connectors. The characterization is performed by measurements in frequency and time domain. The SMA connectors are mounted on microstrip (MS) and conductor-backed coplanar waveguide (CPW-CB) manufactured on high-frequency (HF) laminates. The designed characteristic impedance of the transmission lines is 50 Ω and deviation from the designed characteristic impedance is measured. The measurement results suggest that for a given combination of the transmission line and SMA connector, the discontinuity in terms of characteristic impedance can be significantly improved by choosing the right connector type.

Modelling SMD capacitors by measurements

The lumped models of several capacitors in SMD-0603 package are extracted from S-parameter measurements. The S-parameters of the SMD components are obtained: (i) by modelling the RF connector and transmission lines and de-embedding, and (ii) by directly calibrating the reference plane to the SMD component using on-board calibration standards. The extracted parasitics related to the SMD component package are compared for capacitors of different nominal values and for the two calibration methods in the frequency range up to 8 GHz.

Echo State Networks for Black-Box Modeling of Integrated Circuits

A black-box method for modeling the time-domain response of integrated circuits (ICs) based on echo state networks is proposed. The number and value of the input and feedback delays required for modeling nonlinear systems with memory are detected automatically, and the training procedure is very fast and robust. The resulting models can be implemented in any hardware description language. The proposed modeling approach is applied to three test cases that cover a wide range of analog behavior. The achieved accuracy is comparable to the reference modeling method, and, depending on the complexity of the modeled IC, the simulation speed-up factor is in the order between 10 and 100.

Temperature calibration of an on-chip relaxation oscillator

This work investigates the calibration procedure of a conventional relaxation oscillator. First, the numerical analysis is performed in MATLAB in order to evaluate the sensitivity of the procedure to the noise generated inside the chip and measurement system. Next, the theory is experimentally verified by calibrating four test chip samples designed and manufactured in 0.35-µm CMOS technology. The test chips are calibrated with two different test methods: the first method measures the output frequency in the entire temperature range from −40 to 150 °C during 12 hours; the second method measures the output frequency from 30 to 60 °C during 30 seconds. The proposed calibration methods exhibit the reduction of the frequency error by 18× and 8×, having the total post-calibration precision of ±0.1 % and ±0.22 %, respectively.

Characterization of measurement system for high-precision oscillator measurements

Temperature stability of a high-precision oscillator is characterized by measurements in a temperature chamber. Two time constants are measured for a given temperature of the chamber: (i) time required for the silicon to reach the steady-state temperature obtained by measuring the time-domain voltage response of the on-chip temperature sensor; (ii) time required for the oscillator circuit to reach the steady-state frequency obtained by measuring the oscillator frequency in the time-domain. The temperature probe for measuring the chamber temperature is characterized in terms of its response to a step in temperature. The noise performance of the measurement system is characterized based on Allan deviation.

Design of low-power voltage/current references and supply voltage for 9-bit fully differential ADC

This paper presents the design of a low-power voltage reference, bias current and the supply voltage for a 9-bit fully differential ADC. The references, power supply circuits and the ADC are integrated in one circuit, i.e. chip. The proposed chip is implemented in the UMC 0.18 μm CMOS process and occupies 800×700 μm2. The circuit supply voltage VDD is obtained from the external RF signal. When the circuit is active VDD is used as a supply for the rest of the circuitry. The circuit generates supply, reference voltages and currents when VDD exceeds the upper voltage level VHIGH ≈1.82 V. When VDD is lower than the lower voltage level VLOW ≈1.35 V, the circuit is off. When the circuit is active, the current consumption is 22 μA. The presented results are based on measurements.