Gregor Schatzberger

A Non-Volatile Embedded Memory for High Temperature Automotive and High-Retention Applications

A highly reliable and scalable non-volatile embedded memory cell and technology is described. This embedded technology operates at very low power, and has minimal impact on the analog and digital components used in the SoC design. The main objective of this technology development was to achieve high reliability and high data retention for automotive applications over the extended temperature range from -40deg to 150deg C. A wider range, from -55deg to 180deg C, has been achieved in manufacturing. Full cell, and memory module functionality, and data retention of over 30 years for the automotive temperature range have been achieved. Write cycling of over 200K writes (tested up to 180degC) over the design temperature range has also been achieved. The memory cell and the technology are optimized to operate at very low voltage and consume very low power. The applications requiring high data retention (>50 years), over the industrial or automotive temperature range can be well served with this technology. The data confirms that this technology is a highly manufacturability and a reliable technology for the embedded non-volatile memory applications. The data presented is based on a 0.35mum CMOS technology implementation

Automotive EEPROM Qualification and Cost Optimization

This paper is about how an EEPROM characterization test program for the automotive market was developed for an initial IP Block, introduced into production and then cost and yield optimized for high volume production without risk to quality or reliability.

Efficient contact screening of compact NVMs for high reliabilty automotive applications

In modern automotive designs double contacts are mandatory to achieve high reliability products and avoid field returns due to contact issues during the lifetime of the product. Using double contacts in compact digital IPs like RAM, ROM or NVMs leads to a dramatic area penalty. High area efficient NMVs are using shared contacts to minimize the area needed to realize the NVM bit cells. Using double contacts would lead to an area increase of approx. 50% of the NVM memory plane. The high quality standard defined for automotive applications can only be fulfilled with a sophisticated contact screening procedure. This work will present a contact screening procedure which is able to detect contacts with a resistivity outside the main contact resistivity distribution. Those outlier have a potential danger to fail during lifetime as shown in this paper.

Evidence of erratic behaviors in p-channel floating gate memories and a cell architectural solution

This work shows for the first time the presence of erratic phenomena in p-channel floating gate memories using Fowler Nordheim tunneling for both program and erase operations. A specific p-channel EEPROM architecture is investigated and found to be intrinsically robust against erratic behaviors. A comparison between the p-channel device and a conventional n-channel Flash is discussed and physical interpretations are suggested.

Fully Automatical Test and Qualification System for a High Endurance Embedded EEPROM Module

Qualifying a high temperature, high endurance and high reliability integrated EEPROM process module according the JEDEC and AEC standard needs a large number of tested devices. Correlations of various analog and digital measurements must be done at different supply voltages, temperature conditions and with process variations to ensure a stable high yielding process module. Long program and erase times (milliseconds) for an EEPROM process option result in time consuming measurements. The costs of such a qualification will be comparatively high if all tests are done with production test equipment. Therefore, a test chip concept allowing a wide range of memory sizes was defined for use with a standard PLCC68 package. This package is able to withstand temperatures up to 180degC. Based on the test chip, a parallel, low cost test system was developed enabling the measurement of 96 devices in parallel and hence significantly reducing the test and qualification time and costs.

A 1-MHz on-chip relaxation oscillator with comparator delay cancelation

In this work, an improved topology of a relaxation oscillator is proposed, dealing with the non-idealities of the comparator stage. The oscillator test chips, manufactured in 0.35-μm CMOS process, have the nominal frequency of 1 MHz and typical power consumption of 210 μW. The area of the oscillator core is 0.04 mm2. The measured temperature variation of the output frequency is ±0.4% in the temperature range from −40 to 125 °C. The line sensitivity is 0.28 %/V with the supply ranging from 3.0 to 4.5 V. The output frequency stabilizes after one cycle.

Fast Bit Screening of Automotive Grade EEPROMs—Continuous Improvement Exercise

This paper presents the optimization of an existing electrically eraseable programmable read-only memory (EEPROM) production test flow by means of thorough analysis of the faulty dice and the test flow, which leads to an increase in the yield, a significant decrease in test time, and a decrease in the dppm (increase in quality) level leaving the factory. In order to manufacture high quality and cost-effective EEPROMs suitable for automotive underhood applications, several topics must be taken into account. In addition to a high reliability EEPROM technology, the choice of an advanced memory architecture including error correction code and a highly sophisticated screening methodology in production test is necessary to achieve high quality in the field. The EEPROM production test flow must not only be able to screen out weaknesses in the process but must also be cost efficient. A majority of the tests executed in the EEPROM test flow are needed to check the quality of the processed oxides, which are the basic elements to realize the EEPROM function of the memory. Most of these tests are complex and time-consuming.

Yield improvement of an EEPROM for automotive applications while maintaining high reliability

In order to manufacture high quality and cost effective EEPROMs suitable for automotive under-hood applications several topics must be taken into account. As well as a high reliability EEPROM technology the choice of an advanced memory architecture including ECC and a highly sophisticated screening methodology in production test is necessary to achieve high quality in the field. The EEPROM production testflow must not only be able to screen out weaknesses of the process but must also be cost efficient. A majority of the tests executed in the EEPROM test flow are needed to check the quality of the processed oxides which are the basic elements to realize the EEPROM function of the memory. Most of these tests are complex and time consuming. This work will present an optimization of an existing EEPROM production testflow by means of thorough analysis of the faulty dice and the testflow leading to an increase of the yield without reducing quality.

Relaxation oscillator calibration technique with comparator delay regulation

This paper presents an improved technique for the calibration of the relaxation oscillators with respect to the delay of the comparators. The drawbacks of the conventional topology for the relaxation oscillators are analyzed. Based on the analysis, the circuit modification which resolves the effects of the comparator delay in the trimming procedure is proposed. The simulations in ams 0.18μ CMOS technology exhibit more than 5x the improvement in the precision compared to the conventional topology, evaluated in the temperature range from -40 to 125 °C.

Temperature calibration of an on-chip relaxation oscillator

This work investigates the calibration procedure of a conventional relaxation oscillator. First, the numerical analysis is performed in MATLAB in order to evaluate the sensitivity of the procedure to the noise generated inside the chip and measurement system. Next, the theory is experimentally verified by calibrating four test chip samples designed and manufactured in 0.35-µm CMOS technology. The test chips are calibrated with two different test methods: the first method measures the output frequency in the entire temperature range from −40 to 150 °C during 12 hours; the second method measures the output frequency from 30 to 60 °C during 30 seconds. The proposed calibration methods exhibit the reduction of the frequency error by 18× and 8×, having the total post-calibration precision of ±0.1 % and ±0.22 %, respectively.