Markus Helfenstein

Probability propagation and decoding in analog VLSI

The sum-product algorithm (belief/probability propagation) can be naturally mapped into analog transistor circuits. These circuits enable the construction of analog-VLSI decoders for turbo codes, low-density parity-check codes, and similar codes.

Decoding in analog VLSI

The iterative decoding of state-of-the-art error correcting codes such as turbo codes is computationally demanding. It is argued that analog implementations of such decoders can be much more efficient than digital implementations. This article gives a tutorial introduction to research on this topic. It is estimated that analog decoders can outperform digital decoders by two orders of magnitude in speed and/or power consumption.

An analog VLSI decoding technique for digital codes

Iterative decoding of high-performance error-correcting codes, such as turbo and related codes, is computationally demanding. This paper presents the application of a new type of analog computing network that enables the construction of all-analog decoders for such codes which outperform digital decoders in terms of speed and/or power consumption. The analog networks are based on the observation that certain computations with probabilities are naturally carried out by elementary transistor circuits. As an illustrative example, a complete decoder circuit for a simple tail-biting trellis code is given. Practical implementation issues such as device and thermal mismatch are also discussed.

Baseband and audio mixed-signal front-end IC for GSM/EDGE applications

A complete mixed-signal front-end CMOS chip is presented, supporting GSM/EDGE as well as enhanced audio applications. The chosen solution for the transmit section is based on Laurents approximation of the nonlinear GMSK modulator. This enables burst shaping in the I/Q domain thereby solving the problem of power ramping. Also, up to GPRS class 12 is supported. The receive section on the other hand consists of a low power dual mode continuous-time /spl Sigma//spl Delta/ ADC for I and Q, supporting ZIF and LIF modes of operation and achieving typically 12.5 bit of resolution under production conditions. An on-chip PLL, which supplies all blocks with various clock frequencies, additionally supports clock jitter suppression. The audio section comprises a codec supporting standard formats such as IIS and PCM. It features mono/stereo signaling from various sources in 16bit quality as well as high-drive buffers for 4 /spl Omega/ single-ended loads (capacitively coupled). The whole chip is powered from a 1.5/2.65 V supply voltage and consumes 22 mW in paging mode.

Combined GMSK and 8PSK modulator for GSM and EDGE

An efficient digital GMSK/8PSK I/Q signal modulator for GSM/EDGE is presented. The solution is based on Laurents approximation of the non-linear GMSK modulator by a bank of linear, pre-encoded modulators, thus enabling burst shaping in the I/Q domain and therefore solving the problem of power ramping. The solution is compatible to all major transmitter architectures offering an I/Q interface.

Improved two-step clock-feedthrough compensation technique for switched-current circuits

A new clock-feedthrough compensation scheme for switched-current circuits is proposed. The scheme is especially suited for the design of delay lines for high-frequency operation. The circuit operates by using an improved two-step technique, in which the input is sampled in a parallel combination of a coarse and a fine memory transistor. Since both transistors are of the same type, large switching transients compared to the conventional S/sup 2/I scheme can be avoided. Using the proposed circuit, the coarse memory has considerably more time to settle. Compared to the simple cell, the circuit solution requires only one extra switch and one additional clock phase.

Clockfeedthrough compensation technique for switched-current circuits

A new clockfeedthrough compensation scheme for switched-current systems is proposed. The circuit cancels both the signal dependent and the constant clockfeedthrough term. It is shown that this concept can be used to derive various sample-and-hold circuits, depending on the desired clock frequency, accuracy, and power dissipation. >

90 dB, 90 MHz, 30 mW OTA with the gain-enhancement implemented by one- and two-stage amplifiers

The design of simple gain-enhancement configurations for cascode transistors is presented. Applying one- or two-stage differential amplifiers, or an improved regulated cascode configuration in the feedback loop of a cascode, allows high speed and high gain super-transistors at low voltage to he designed. These concepts were implemented in a symmetrical OTA resulting in a measured 90 dB, 90 MHz, 30 mW amplifier performance for a 14 pF load. Settling measurements to 0.1% error for a unity-gain configuration are presented.

Distortion analysis of switched-current circuits

A distortion analysis based on the large signal behavior of the basic switched-current memory cell is presented. In the first part, based on a closed form solution of the step response, distortion due to the settling error is addressed. In the second part, distortion caused by clock-feedthrough is analysed. The solutions are compared with simulated and/or measured results. Furthermore, harmonic terms above the fifth are shown to be negligible.

Design techniques for HDTV switched-current decimators

The design of switched-current decimators for wide bandwidth video filtering applications is presented. Applying topologies with only one input commutator to switched-currents allows the design of high speed polyphase input branches with reduced distortion. These concepts were utilized in the implementation of a linear phase 19 tap FIR filter chip with an amplitude response tailored to video applications. It is expected that the prototype filter implemented in a 0.5 /spl mu/m CMOS process will operate at an input sampling rate of 135 MHz and with a decimating factor of 5.