Markus Holzer

Optimized hardware architecture of a smart camera with novel cyclic image line storage structures for morphological raster scan image processing

In this work we present an FPGA (Field Programmable Gate Array) based smart camera framework with a multiport cyclic image line storage structure and an optimized architecture for morphological raster scan image processing. The signal processing architecture is able to reuse intermediate results of 2D morphological operations, can handle different shapes of structuring elements and uses only a minimum amount of FPGA logic and block RAM resources for intermediate image line storage. This combination allows the output of one processed pixel per clock cycle and hence, build the fundament for a system architecture, which provides high frame rates with low system delays.

Application of kalman filters as a tool for phase and frequency demodulation of IQ signals

Frequency or phase modulated electrical signals arise in multiple applications in communication systems as well as in measurement setups such as interferometry / vibrometry, velocimetry etc. common demodulation techniques are often based on analog techniques (e.g. a PLL in the RF band) or - after mixing into the base band and generating IQ signals - on digital signal processing algorithms.

Orthogonal shift level comparison reuse for structuring element shape independent VLSI-Architectures of 2D morphological operations

In this work we present an efficient and flexible - structuring element shape independent - new VLSI-architecture design approach for 2D morphological operations. Contrary to common used architecture design concepts based on structuring element areal decomposition is the ability to handle arbitrary non-convex flat structuring elements. Furthermore, no intermediate image data storage over several image lines is required and the amount of comparators and registers is reduced by reusing results on so called orthogonal shift levels. This leads to efficient realizations regarding hardware complexity and maximum clock frequency.

A real time video processing framework for hardware realization of neighborhood operations with FPGAs

In this work we present a real time video processing framework, which can handle high data throughput rates. Contrary to common digital hardware realizations which use several image line long shift register pipelines for direct calculation of 2D neighborhood operations, we suggest an efficient cyclic image line storage structure by using dual port block RAM buffers, which are available in recent FPGAs. Therefore, our approach does not occupy a huge amount of valuable logic resources in the FPGA for shift registers based data storage and achieves a high data throughput by parallel video data processing paths. With this memory structure we realize — already principally proposed in a previous work — a new hardware architecture of the basic morphological image processing operations erosion and dilation as building blocks. With these building blocks, which are hardware occupation and maximum clock frequency efficient, we also implemented the combined morphological operations opening and closing, which are commonly used for image enhancement like noise reduction and object contour smoothing.

Aspects of Signal Processing in Laser Vibrometry and their Embedded-Realisation on FPGA with NI-LabVIEW

The most common approach in todays interferometric laser vibrometry is the so called heterodyne technique. This about 20 year-old method works with two optical beams with two different optical frequencies that are lead over separate ways and, after one of them has interacted with the vibrating target, are superimposed on optical detectors to produce interference signals [1] However, this concept requires expensive optical components such as a Bragg Cell or a Zeeman-Laser. In order to reduce the manufacturing cost of an interferometic laser vibrometer we persecute a strategy which reduces the optical complexity for the prize of higher signal processing demand. Based on the fact that today highly integrated signal processing hardware such as DSPs (Digital Signal Processors) FPGAs or ASICs solutions are much less expensive than in the past, this so called HWSHD (Homodyne With Synthetic Heterodyne Demodulation) strategy is therefore competitive to the classical usage of expensive optical components in the heterodyne concept. This paper will, after a brief introduction into the homodyne vibrometer concept, describe the idea and realisation aspects of the signal processing algorithm by usage of NI-LabVIEWs FPGA Module.

Modeling and code generation of recursive algorithms with extended UML Activity Diagrams

While most current graphical modeling languages for specifying digital signal processing algorithms provide a rich set of loop techniques and execution semantics based on IP-libraries, they lack in general of the flexibility of model based development frameworks. Also, the potential of recursive and repetitive graphical descriptions is mostly not utilized. We present a novel graphical notation to describe digital signal processing systems which enables the general specification of repetitive and recursive algorithms with hierarchical and parallel behavior diagrams. Our approach closes also the gap to flexible model-driven approaches by using extended UML Activity Diagrams, which enable the use of model based techniques including abstract descriptions, model-to-model-transformations and code generation for rapid prototyping of hardware and software systems.

Critical path minimized raster scan hardware architecture for computation of the Generalized Hough Transform

The Generalized Hough Transform (GHT) is a well known image processing transform to find arbitrary shapes in images. We propose a new raster scan FPGA and VSLI hardware architecture, performing the GHT of a binary template shape with an input image. The architecture has a minimized critical path by the reuse of partial results and the utilization of a flat adder structure. A synchronous pixel pipeline for input image row buffering enables parallel read and write access of the partial results. By this, the architectures critical path and hence the maximum clock frequency is independent of the template size, content and number of valid pixels in the template. The architecture was implemented on a Xilinx Virtex 5 FPGA device. The design reaches a pixel clock of more than 580 MHz at an exemplary image size of 512×512 pixels and a template size of 64×64 pixels.

Shape independent VLSI-architecture design approach for 2D morphological operations with non-flat structuring elements

In this work we present a structuring element shape independent Very Large Scale Integration (VLSI) design approach for 2D morphological operations, which is capable to handle flat and non-flat structuring elements. Contrary to other architectural concepts which are commonly based on structuring element areal decomposition and a sequential calculation approach, our approach requires no intermediate image data storage over several image lines. In addition, the amount of comparators, registers and for non-flat structuring elements adders / subtractors is reduced significantly by reusing results on so called orthogonal shift levels. This leads to hardware efficient and fast VLSI realizations of 2D morphological operations.