Thomas Greiner

Symmetry-based face pose estimation from a single uncalibrated view

In this paper, a geometric method for estimating the face pose (roll and yaw angles) from a single uncalibrated view is presented. The symmetric structure of the human face is exploited by taking the mirror image (horizontal flip) of a test face image as a virtual second view. Facial feature point correspondences are established between the given test and its mirror image using an active appearance model. Thus, the face pose estimation problem is cast as a two-view rotation estimation problem. By using the bilateral symmetry, roll and yaw angles are estimated without the need for camera calibration. The proposed pose estimation method is evaluated on synthetic and natural face datasets, and the results are compared with an eigenspace-based method. It is shown that the proposed symmetry-based method shows performance that is comparable to the eigenspace-based method for both synthetic and real face image datasets.

Optimized hardware architecture of a smart camera with novel cyclic image line storage structures for morphological raster scan image processing

In this work we present an FPGA (Field Programmable Gate Array) based smart camera framework with a multiport cyclic image line storage structure and an optimized architecture for morphological raster scan image processing. The signal processing architecture is able to reuse intermediate results of 2D morphological operations, can handle different shapes of structuring elements and uses only a minimum amount of FPGA logic and block RAM resources for intermediate image line storage. This combination allows the output of one processed pixel per clock cycle and hence, build the fundament for a system architecture, which provides high frame rates with low system delays.

Orthogonal shift level comparison reuse for structuring element shape independent VLSI-Architectures of 2D morphological operations

In this work we present an efficient and flexible - structuring element shape independent - new VLSI-architecture design approach for 2D morphological operations. Contrary to common used architecture design concepts based on structuring element areal decomposition is the ability to handle arbitrary non-convex flat structuring elements. Furthermore, no intermediate image data storage over several image lines is required and the amount of comparators and registers is reduced by reusing results on so called orthogonal shift levels. This leads to efficient realizations regarding hardware complexity and maximum clock frequency.

A Systematic Approach for Synthesizing VLSI Architectures of Lifting-Based Filter Banks and Transforms

The lifting scheme has become an important tool for designing filter banks and transforms of digital signal processing. Recently, the conventional lifting scheme that concerns the construction of 2-channel filter banks has been extended to M-channel filter banks (M > 2), bringing up the desirable properties of the lifting scheme to a broader range of applications. Many hand-crafted lifting-based VLSI architectures exist, which mostly concentrate on a single and specific target application having fixed data throughput and resource consumption. However, the reusability of such architectures is limited due to the lack of scalability. To overcome this issue, we present a design methodology for automatic synthesis of VLSI architectures suitable for arbitrary lifting-based M -channel filter banks and transforms. The proposed methodology enables high parameterizability in terms of data throughput, resource consumption, and arithmetic precision for the generated architectures. The concept of parameterizing design elements is important for modern system-on-chip design, since it features design space exploration and increases reusability. The proposed methodology is implemented as a high-level compilation tool that generates VLSI architectures at the register transfer level. We present results on the implementation of different architectures that were generated by our tool.

Matching cost computation algorithm and high speed FPGA architecture for high quality real-time Semi Global Matching stereo vision for road scenes

Stereo correspondence and the generation of the disparity map, which encodes the depth of objects, is one of the most challenging and important tasks for camera based environment perception systems. Thus, it is indispensable for autonomous driving vehicles and transportation devices to detect other cars or for the classification of obstacles. To enable this, relatively large real world images must be processed at high data rates. At the moment, Semi Global Matching (SGM) is the most promising approach for the stereo matching of real world images at sufficient quality and the capability of high data rates. Real-time SGM implementations on small image sizes have been reported, however, current stereo camera image sizes pose still high computational complexity and memory demand for SGM. This paper describes a new method for the efficient computation of stereo matching costs to reduce the complexity and the high memory demand for cost volume and cost aggregation buffering. Using the proposed complexity reduction, we present modules and concepts for full parallel FPGA implementations of the cost volume creation, SGM aggregation and disparity selection. We evaluate the presented algorithm using the KITTI stereo vision benchmark and achieve, besides competitive quality results, a data throughput for the cost calculation of 199 frames per second (fps) for an image size of 1242 × 375 with a disparity range of D = 160 and tremendously reduced memory requirements.

A real time video processing framework for hardware realization of neighborhood operations with FPGAs

In this work we present a real time video processing framework, which can handle high data throughput rates. Contrary to common digital hardware realizations which use several image line long shift register pipelines for direct calculation of 2D neighborhood operations, we suggest an efficient cyclic image line storage structure by using dual port block RAM buffers, which are available in recent FPGAs. Therefore, our approach does not occupy a huge amount of valuable logic resources in the FPGA for shift registers based data storage and achieves a high data throughput by parallel video data processing paths. With this memory structure we realize — already principally proposed in a previous work — a new hardware architecture of the basic morphological image processing operations erosion and dilation as building blocks. With these building blocks, which are hardware occupation and maximum clock frequency efficient, we also implemented the combined morphological operations opening and closing, which are commonly used for image enhancement like noise reduction and object contour smoothing.

Fault-tolerant strategies for double three-phase PMSM used in Electronic Power Steering systems

Safety-critical applications like Electronic Power Steering (EPS) systems demand highest reliability of electrical drives in automotive applications. Based on safety standards and associated requirements, the availability can be raised significantly through redundant system structures. In case of critical faults complete loss of steering assistance can be prevented by using different control methods and drive strategies adapted to the redundant structure. This paper shows fault-tolerant strategies for a double three-phase Permanent Magnet Synchronous Motor (PMSM) with independent motor windings and redundant voltage source inverters. Due to the redundant system structure and depending on critical faults it is possible to implement fault-tolerant methods. Fault compensation measures are discussed, making clear how unwanted effects on the steering torque can be contained. The new fault-tolerant strategies were performed on EPS systems to support fail-operational mode taking into account safety requirements.

Two-Stage Orchestration Approach for Plug and Produce Based on Semantic Behavior Models

Due to changing requirements and increasing engineering efforts of manufacturing systems, methods such as plug and produce gain in importance. The ability to adapt to varying product variants and new manufacturing modules can be achieved through cyber-physical production systems. In this context orchestration, the process of selecting suitable manufacturing modules, is a major aspect. Current approaches mostly focus on a functionality matching, not taking into account continuous system aspects such as throughput or energy consumption. This paper presents a two-stage orchestration approach for modular cyber-physical production systems. The manufacturing modules are semantically described regarding their functionality, system interfaces and continuous system behavior. Based on a high-level production process specification, possible variants of actual manufacturing systems are determined. The orchestration algorithm uses weighted scoring functions to calculate the matching degree and thereby enables a ranking. In order to match continuous system behavior and to use it as criterion for orchestration, Semantic Behavior Models (SBM) are introduced.

Software architecture for cyber-physical control systems with flexible application of the software-as-a-service and on-premises model

In this paper a new software architecture is introduced which combines and adapts effective design patterns for the development of cloud-based algorithms in cyber-physical control systems (CPCS). The integration of cloud computing and cyber-physical systems (CPS) allows the flexible use of IT-Services and offers nearly infinite amount of storage space and computing capacities for embedded systems. With capable cloud-based algorithms, enhanced and situation-related decisions become possible without a need for scaling the computing capacities of the embedded system itself. Further advantages are the easy integration of third-party data-sources into cloud-based algorithms and the flexible development of control algorithms in high-level programming languages like Java.

Debugger-Based Record Replay and Dynamic Analysis for In-Vehicle Infotainment

In the first operation tests of In-Vehicle Infotainment systems remaining failures which were not detected by other testing techniques can often be observed. These failures have to be reconstructed in the laboratory in order to be able to debug them. Record and replay concepts enable the automatic reconstruction of execution sequences, but often they disturb the normal execution, require comprehensive instrumentation or can not be implemented for every platform. Our approach considers these criteria by implementing record and replay with a symbolic debugger. Manually locating the root causes of failures during replay is time-consuming. Therefore, we apply dynamic analyses; they can detect anomalies and state changes during a run. The paper presents a collection of analyses which can not be smoothly executed online during operation, but do not cause drawbacks at replay.