Markus Pfeffer

From overall equipment efficiency (OEE) to overall Fab effectiveness (OFE)

Abstract The metrics of the SEMI standard E79 offers a good method to calculate the overall equipment efficiency (OEE) and finds increasing application and acceptance in the semiconductor industry. To effectively apply E79, communication with the host using the SEMI SECS and GEM standards is required. Beyond the application of the communication standards, equipment models for the different tools and especially for cluster tools have to be created. Up to now, there are no standardized OEE models available. The paper will give examples of modeling methods, models, and also of software tools for the calculation and monitoring of OEE. However, successful analysis on OEE only is not sufficient as no machine is isolated in a factory, but operates in a linked and complex environment. A wider approach has to focus also on the performance of the whole factory. The characterization of a semiconductor factory by qualified metrics is rather complicated and difficult. So far, no standardized methods and metrics are available. Different methods and metrics introduced in the literature are presented in the paper. All methods have in common that they do not directly consider the costs. Including cost analysis would require the use of metrics for characterization of overall Fab effectiveness (OFE) in order to obtain a result for the cost per die out.

Framework for integration of virtual metrology and predictive maintenance

Within the ENIAC project “IMPROVE”, new algorithms for virtual metrology and predictive maintenance are being developed to substantially enhance efficiency in European semiconductor manufacturing. The consortium comprises important IC manufacturers in Europe, solution providers, and research institutions. A major objective of the project is to make these new APC methods applicable in the existing fab systems of the IC manufacturers which widely differ in the automation infrastructure. A novel framework architecture for integration of the new control paradigms was researched and a software for implementation of the framework was developed. This paper describes the technical details and results of the framework development, implementation, and test.

Comparison of Silicon Surface Preparation Methods for Measurement of Minority Carrier Lifetime using the Microwave Photo-conductive Decay (μ-PCD) coupled with Continuous Corona Charge (Charge-PCD)

Microwave-Photoconductive Decay (μ-PCD) is a well known method for measurement of carrier lifetimes in silicon (1). In the manufacturing process of pure silicon for microelectronics or solar PV the main purpose for measurement of the minority lifetime is the determination of impurities which act as lifetime “killers”. The metal iron is a common contaminant and in p-type material forms Fe-B pairs which can be dissociated by high intensity flashes or laser illumination. Dissociation causes a change in the lifetime, and from this change the iron contamination can be readily determined (2).

Contamination Control for Wafer Container Used within 300 mm Manufacturing for Power Microelectronics

This paper gives an overview about all activities performed within a common project between industrial and academic partners to define clean room concepts for the first worldwide high volume semiconductor front end facility IFD for 300 mm power semiconductors. The investigation within this study is the base for the 300 mm container strategy resulting in new innovative manufacturing and automation concepts.

Advanced contamination control methods for yield enhancement

Semiconductor manufacturing is a highly complex process, with a high need for process control, but equally important are effective methods for contamination control during and after the processes. Methods for detection of airborne and surface molecular contaminants were developed to meet the challenging requirements for More Moore and More than Moore applications. Qualitative and quantitative contamination analysis of organic and inorganic compounds allows monitoring of contamination in front- as well as back-end processes. In this way, cross contaminations including precious metals, e.g. Au, Ag, Pd, organic and inorganic compounds e.g. sulfur, fluorine can be avoided. By the use of state-of-the-art analytical systems, a contamination control for any cleanroom and all wafer sizes could be implemented.

Performance Optimization of Semiconductor Manufacturing Equipment by the Application of Discrete Event Simulation

Semiconductor wafer fabrication facilities (wafer fabs) are amongst the most complex production facilities. State-of-the-art wafer fabs comprise a large product variety, hundreds of processing steps per product, almost hundreds of machines of different types, and automated transportation systems combined with reentrant flows throughout the fab. In addition to the high complexity, wafer fabs require very high capital investment and an undisturbed operation. Semiconductor manufacturers are facing fierce competition as more global capacity is being added. Through this intense competition, semiconductor manufacturers have to improve their processes from a technological as well as from a logistical point of view in order to be successful within the global market. The logistics not only involves fab wide optimization strategies but also the individual equipment performance, for example cycle time and throughput, has to be considered. In this paper, the need for performance optimization of semiconductor manufacturing equipment is identified and the capability of discrete event simulation for such optimizations is being elaborated. Characteristics of different types of simulation models are described and the simulation model selection is explained. For case studies, several simulation models of different semiconductor manufacturing equipment have been developed. Using five examples, different optimization strategies, dependent on the application of the semiconductor manufacturing equipment, have been investigated by discrete event simulation. The paper shows the influence of the integration of metrology into deposition equipment, the impact of different batch sizes for oxidation processes, and the optimized dimensioning of photolithography equipment. Furthermore, the throughput and cycle time of different deposition equipment are optimized by the evaluation of various improvement strategies. All investigations have been performed with real data extracted from already utilized equipment or at least with data from the equipment suppliers of prototype equipment.Copyright

Enhanced contamination control methods in advanced wafer processing

Semiconductor manufacturing is a highly complex process, with a high need for process control, but equally important are effective methods for contamination control. Methods for detection of airborne and surface molecular contaminants were enhanced to meet the increasing requirements for future More Moore and More than Moore applications. Improved qualitative and quantitative contamination analysis methods of organic and inorganic compounds allow exact monitoring of contamination in front- as well as back-end processes. By the use of state-of-the-art analytical systems combined with validated analytical procedures and advanced sample preparation techniques contamination analytical results with higher reproducibility and reliability are being ensured.

Advanced detection method for polymer residues on semiconductor substrates: 3D/TSV/interposer: Through silicon via and packaging

A novel inspection technology for detection of thin polymer layers, deposited on structured silicon wafer surfaces, has been developed. The labeling of polymer residues with fluorophore combined with the subsequent examination under a fluorescence microscope enables a non-destructive detection of amorphous and semi-crystalline polymers and polymer residues on wafer substrates.

Particle Free Handling of Substrates

Semiconductor technology is heading towards the 10 nm node and even smaller in the coming years. This development relies not only on new process technologies, like lithography techniques, but also on safer and cleaner handling techniques that meet the high-end requirements of the production line. In this paper, the evaluation of different end-effectors and handling techniques regarding particle generation, organic and metallic contamination effects will be discussed. Bernoulli, carbon and standard vacuum end-effectors are being tested and compared with each other for the handling of 200 mm and 300 mm wafers.

Particle free handling of substrates

Semiconductor technology is heading toward the 10 nm node and even smaller in the coming years. This development relies not only on new process technologies, like lithography techniques, but also on safer and cleaner handling techniques that meet the high-end requirements of the production line. In this paper, the evaluation of different end-effectors and handling techniques regarding particle generation, organic, and metallic contamination effects will be discussed. Bernoulli, ultrasonic, carbon, and standard vacuum end-effectors are being tested and compared with each other for the handling of 300 mm wafers.