Markus Schwerd

Comparison of copper damascene and aluminum RIE metallization in BICMOS technology

Modern interconnect schemes will be using copper instead of aluminum as metallization material due to its better electrical conductivity and its superior electromigration resistance. Using a production worthy BICMOS process it could be revealed that especially for this kind of application a copper dual damascene metallization offers serious advantages versus an aluminum RIE/tungsten plug approach. Interconnect parameters which are very helpful for high-performance RF technologies like line and via resistances can be reduced showing equal leakage current properties. Current density can be increased and up to now no impact on Bipolar and only slight influence on CMOS devices, which needs to be investigated in more detail, is detected.

Copper Contamination effect on the reliability of devices in the BiCMOS technology.

Copper (Cu) will be used to replace aluminum in the next generation metallization due to its low resistivity and high electromigration resistance. However, copper is a fast diffuser in silicon and silicon dioxide, and it is detrimental to the devices if it gets into the active region. We have investigated several approaches to contaminating with Cu the back surface of a fully processed BiCMOS wafer in order to study its effect on devices. In order to estimate the amount of Cu driven to the active region, a simulated drive-in diffusion experiment is used. Vapor Phase Decomposition--Atomic Absorption Spectrometry is used to measure Cu on the front surface of the wafer after annealing. In a fully processed BiCMOS wafer, the internal gettering: oxygen precipitation occurs at the initial high temperature process steps. This oxygen precipitation acts as trapping centers and an intrinsic barrier that prevents impurities that may be driven from the back surface of the wafer. The effectiveness of the internal gettering of a simulated BiCMOS processed wafer is measured in comparison to a monitor wafer which has no internal gettering. Electrical measurement shows an increase in the base current in a Gummel Plot measurement of the Bipolar device after Cu contamination. This effect is most visible for a wafer that has been annealed at 550 degree(s)C for 30 minutes.

Reliability degradation of MOS transistors originated from plasma process-induced charging of circuit blocks and detected with fWLR methods

The effect of plasma process induced charging of remote circuit blocks and consequently the reliability damage on a single MOS transistor which is connected to such a circuit block is demonstrated for the first time. Traditional methods of characterizing gate electrode antennas do not cover this topic. A new product relevant plasma-induced damage test structure type is introduced as well as a new definition of the antenna ratio to describe the damage potential of a circuit block. This investigation is carried out for a standard 130nm bulk-Si technology with a deep trench process.

Optimized data assessment for hot carrier and Fowler-Nordheim stresses on thick MOS gate oxides with plasma process induced charging damage

In this work experimental data of thick MOS gate oxides (25 nm) of a state of the art 90 nm technology are assessed for degradation from plasma induced charging (PID). It is demonstrated that the type of stress measurement and the data analysis approach are crucial for the interpretation of the experimental data and for lifetime estimation. Two PID stress measurements are compared: hot carrier stress and Fowler-Nordheim stress. Different data analysis concepts illustrate that the usual technique can give misleading analysis results, just calculating the drift of MOS transistor parameters. It is shown that the type of PID protection for MOS transistor test structures plays a significant role in the misinterpretation of MOS device data.

Quantitative reliability assessment of Plasma Induced Damage on product wafers with fast WLR measurements

This paper describes the assessment of a plasma induced damage (PID) event in the metal stack of an 8 inch 130 nm process line. The relevant PID stress and measurement sequence used, during standard productive fast wafer level reliability (fWLR) monitoring, which had detected this event, is discussed, and it is shown to be very effective. Additionally, hot carrier stress was performed on MOS transistors with antenna structures connected to the gate electrode for the quantification of the PID effect. It is demonstrated that the complete investigation can be done on productive wafers in a very short time and only on scribe line test structures, saving time and and extra wafer cost.