Martina Hommel

Highly accelerated electromigration lifetime test (HALT) of copper

The reliability of copper interconnects is an important aspect in ULSI technology. The test time of the standard electromigration test is rising with improving interconnect systems. At moderate current densities, lifetime test could last more than 500 h. In this paper, lifetime tests on via-line test structures in a copper dual-damascene technology at extremely high temperatures have been investigated. This method is an alternative solution to the well-known SWEAT method where high current densities are used to accelerate the lifetime test. The used test system was a modified Suss probe station with a self-made reactor. The results have been compared with standard tests performed in commercial oven test equipment. Bimodal behavior was observed above 425/spl deg/C. Only one of the two observed failure types shows the expected thermal dependency and can be extrapolated to the standard test temperatures with Blacks equation. The estimated activation energy E/sub A/=0.81 eV is comparable to the activation energy determined by standard tests below 350/spl deg/C. The benefit of this method is a reduction in test time of more than a decade at 425/spl deg/C in comparison to the standard test at 300/spl deg/C and a moderate current density.

Stress-induced voiding in aluminum and copper interconnects

Stress-induced voiding (SIV) is a serious reliability problem in metal interconnects. For aluminum a phenomenological model was developed which allows the extrapolation of metallization life times from stress conditions to operation conditions of the integrated circuit. Resistance drift measurements during high-temperature storage (HTS) on wafer-level have been performed and the experimental data could be fitted with that model. The influences of different parameters such as line width, metal level, thermal anneals of certain metal levels during processing and the deposition temperature of the interlevel dielectric material on the SIV behavior are discussed. The SIV behavior of copper dual damascene metallizations has been investigated on via line structures. A linear resistance drift during high-temperature storage has been observed. This is in contrast to aluminum, where a non-linear behavior was found. Failure analysis showed voids inside the via and not in the metal line as it has been observed in aluminum. Stress simulations have been performed in order to explain this behavior. Due to the complex stress state in a copper dual damascene via the temperature dependence of SIV in copper is different from that of aluminum.

Size Effects and Temperature Dependence of Stress-Induced Voiding

In this investigation the stress-induced voiding (SIV) behavior of via structures with different geometries was tested. A variation of via sizes, aspect ratios, and widths of connected metal lines was studied. The resistance drift and its temperature dependence behavior showed sensitivity to the structure size. This can be explained by the size-dependence of mechanical stress in the metallization

Stress induced metallurgical effects in Ti/TiN/AlCu/TiN metal stacks

Integrated circuits with aluminum metallization for products with high current densities need a metal stack with liner and antireflective coating (ARC) which can fulfill several requirements (e.g. low sheet resistance, high reliability, smooth surface, good adhesion, thermal stability, etc.). In this work different multilayer metal stacks are investigated and several phenomena which can be observed after thermal annealing of Ti/TiN/AlCu/TiN stacks are described and discussed. Metallurgical, electrical and mechanical properties of different layer combinations are investigated after thermal annealing and stress tests are done to compare the electromigration and life time behavior of each metal stack. For all investigated metal stacks it is shown that an interface reaction between Ti and aluminum will form TiAl3 phase. Even with very thick TiN layers on top of titanium or with only TiN liner the phase formation occurred. Explanations and models for the formation of different phenomena (hillocks, depressions ...

A new built-in screening methodology for Successive Approximation Register Analog to Digital Converters

A novel built-in approach is proposed to screen out defects in the array of capacitors and control logic of Successive Approximation Register Analog to Digital Converters. This technique is based on an embedded circuitry for the configuration, the stressing and for an accurate and fast leakage current measurement. The built-in screening system reduces the dependency on external automatic test equipment and cuts the testing time and costs. The proposed solution has been integrated on silicon for verification and characterization. The idea implies a negligible silicon area overhead because the test structure can be shared among multiple Analog to Digital Converters on the same chip.