Marly Roncken

The VLSI-programming language Tangram and its translation into handshake circuits

Views VLSI design as a programming activity. VLSI designs are described in the algorithmic programming language Tangram. The paper gives an overview of Tangram, providing sufficient detail to invite the reader to try a small VLSI program himself. Tangram programs can be translated into handshake circuits, networks of elementary components that interact by handshake signaling. The authors have constructed a silicon compiler that automates this translation and converts these handshake circuits into asynchronous circuits and subsequently into VLSI layouts.<<ETX>>

Asynchronous circuits for low power: a DCC error corrector

The authors describe a complete low-power digital compact cassette error corrector. Using Tangram, a high-level programming language, they designed two asynchronous circuits that correct errors on DCC specifications.<<ETX>>

An asynchronous instruction length decoder

This paper describes an investigation of potential advantages and pitfalls of applying an asynchronous design methodology to an advanced microprocessor architecture. A prototype complex instruction set length decoding and steering unit was implemented using self-timed circuits. [The Revolving Asynchronous Pentium/sup (R)/ Processor Instruction Decoder (RAPPID) design implemented the complete Pentium II/sup (R)/ 32-bit MMX instruction set.] The prototype chip was fabricated on a 0.25 /spl mu/m CMOS process and tested successfully. Results show significant advantages - in particular, performance of 2.5-4.5 instructions per nanosecond - with manageable risks using this design technology. The prototype achieves three times the throughput and half the latency, dissipating only half the power and requiring about the same area as the fastest commercial 400 MHz clocked circuit fabricated on the same process.

A single-rail re-implementation of a DCC error detector using a generic standard-cell library

We present a fully asynchronous implementation of a DCC Error Detector. The circuit uses 4-phase handshake signaling and single-rail data encoding, and has been realized using standard cells from a generic cell library. The circuit is obtained by fully automatic translation from a high-level (Tangram) description, using handshake circuits as intermediate architecture. In comparison with a previous double-rail implementation the fabricated IC is 40% smaller (core area), three times faster, and consumes only a quarter of the power. Switching between two power supplies is described as a technique to reduce power dissipation even further. A comparative evaluation also includes an improved double-rail implementation and two synchronous circuits.

Partial scan test for asynchronous circuits illustrated on a DCC error corrector

We present a design-for-testability method for asynchronous circuits based on partial scan. More specifically, we investigate how the partial scan principles from the synchronous test world can be adapted to asynchronous circuits, and we show that asynchronous partial scan design can be approached as a high-level design activity. The method is demonstrated on an asynchronous error corrector for the DCC player. It has been used effectually in the production and application-mode tests of this 155 k transistor chip-set. In particular, it has led to high 99.9% stuck-at output fault coverage in short 64 msec test time at the expense of less than 3% additional area.

An error decoder for the Compact Disc player as an example of VLSI programming

Using a programming language for VLSI design, called Tangram, they design a fast and simple VLSI circuit for error decoding in the Compact Disc player. The derivation of the design is straightforward and the result is succinctly expressed in less than one page of Tangram text. All design decisions are based merely on algorithmic and architectural considerations. No particular VLSI knowledge is needed and, therefore, the exercise demonstrates that Tangram allows system designers to design VLSI circuits. The exercise also shows that in a VLSI programming language special language constructs are essential to obtain efficient designs.<<ETX>>

Optimal scan for pipelined testing: an asynchronous foundation

This paper addresses the problem of constructing a scan chain such that (1) the area overhead is minimal for latch-based designs, and (2) the number of pipeline scan shifts is minimal. We present an efficient heuristic algorithm to construct near-optimal scan chains. On the theoretical side, we show that part (1) of the problem can be solved in polynomial time, and that part (2) is NP-hard, thus precisely pinpointing the source of complexity and justifying our heuristic approach. Experimental results on three industrial asynchronous IC designs show (1) less than 0.1% extra scan latches for level-sensitive scan design, and (2) scan shift reductions up to 86% over traditional scan schemes.

Test quality of asynchronous circuits: a defect-oriented evaluation

This paper investigates the test quality of asynchronous circuits using fault models that are grounded in realistic defect probabilities. As for synchronous designs, I/sub DDQ/ testing plays a prominent role in detecting CMOS manufacturing defects for asynchronous designs, too. However, for asynchronous circuits, I/sub DDQ/ testing is usually less effective because fewer states are quiescent, and our analysis shows that the test quality can only be improved by creating more quiescent states. We present a new Design-for-Test (DfT) method that provides good test quality in that all defects are detected that are likely to occur given the IC layout and process technology and that pose quality or reliability problems. Our DfT method is evaluated on three in-house manufactured designs.

Defect-oriented testability for asynchronous ICs

For a CMOS manufacturing process, asynchronous ICs are similar to synchronous ICs. The defect density distributions are similar, and hence, so are the fault models and fault-detection methods. So, what makes us think that asynchronous circuits are much harder to test than synchronous circuits? Because the effectiveness of best known test methods for synchronous circuits drops when applied to asynchronous circuits? They may very well be a temporal hurdle. Many test methods have already been reevaluated and successfully adapted from the synchronous to the asynchronous test domain. The paper addresses one of the final hurdles: I/sub DDQ/ testing. This type of test method, based on measuring the quiescent power supply current, is very effective for detecting (resistive) bridging faults in CMOS circuits. Detection of bridging faults is crucial, because they model the majority of todays manufacturing defects. I/sub DDQ/ fault effects are sensitized in a particular state or set of states and can only be detected if we stop the circuit operation right there. This is a problem for asynchronous circuits, because their operation is self-timed. In the paper, we quantify the impact of self timing on the effectiveness of I/sub DDQ/-based test methods for bridging faults, and propose a Design-for-Test (DfT) approach to develop a low-cost DfT solution. For comparison, we do the same for logic voltage testing and stuck-at faults. The approach is illustrated on circuits from Tangram, the asynchronous design-style employed at Philips Research, but it is applicable to asynchronous circuits in general.

A fully-asynchronous low-power error corrector for the DCC player [CMOS technology]

The promise of chip-wide asynchronous operation is its potential for very low power consumption. This potential is demonstrated by an error-corrector based on digital compact cassette (DCC) specifications, dissipating 80% less than its synchronous counterpart. A reduction in power consumption means longer battery lifetime, important in portable products such as cellular radio and personal audio.<<ETX>>