Ivan E. Sutherland

Circuit Techniques to Enable 430Gb/s/mm2 Proximity Communication

Two chips communicate over a capacitively-coupled I/O link at 1.8Gb/s/ch. Channels are placed on a 36mum pitch. 144 channels operate simultaneously for an aggregate bandwidth of 260Gb/s, or 430Gb/s/mm2 in 0.18mum CMOS. Measured energy consumption is 3.0pJ/b and BER is <10-15. Electronic alignment and crosstalk rejection allow reliable I/O for practical implementation

Predicting performance of micropipelines using Charlie diagrams

A technique is presented to predict the performance behavior of control circuits for a linear FIFO. The control circuit consists of a linear chain of RendezVous elements, also called JOINs, preceded by a source and followed by a sink. The technique predicts how the cycle time, or throughput, of the FIFO depends on the sink delay, the source delay, and the length of the FIFO. It also predicts how the delays in each RendezVous element depend on the same set of parameters. The pipelines can be divided into three cases: source-limited, sink-limited, and self-limited pipelines. The technique is based on the assumption that the delays through a RendezVous element can be described as a function of the separation in arrival times of the inputs. Such descriptions are conveniently represented by the so-called Charlie diagram.

FLEETzero: an asynchronous switching experiment

This paper describes a working chip, called FLEETzero, built to test an asynchronous switch fabric. The switch fabric transports 8-bit data items from any of eight sources to any of eight destinations. Measured throughput corresponds to approximately six gate-delays per data item, which in its 0.35 micron technology is in excess of 1.2 Giga-Data-Items per second (GDI/s); the corresponding latency through seven stages from source to destination is less than 4 nanoseconds. FLEETzero demonstrates a new family of high speed asynchronous control circuits, especially data-controlled branch and merge circuits that form the switch fabric. The FLEET concept may also herald a paradigm shift for computers. This new paradigm emphasizes data movement as the core action and contrasts with the traditional op code paradigm that focuses attention on logic and arithmetic instructions. The new paradigm promises outstanding throughput and many opportunities for optimization.

GasP control for domino circuits

We present two novel asynchronous control circuits for domino pipelines. The control circuits are based on GasP circuits, have a minimum cycle time of six gate delays, and compare favorably with previously published control circuits. We present some results from a chip implementation of several 64-bit domino adders in a TSMC CMOS 180 nm process technology.

New division algorithms by digit recurrence

This paper offers two new division algorithms by digit recurrence. Compared to the standard radix-2 division algorithms with carry-save addition, the new division algorithms trade off a simpler selection logic for more alternatives in the basic repetition step. Our final division algorithm is potentially faster and more energy efficient than radix-2 division with carry-save addition, because the selection logic has less delay and the repetition steps on average perform fewer additions and subtractions.

A comparison of codebook generation techniques for vector quantization

The paper examines tradeoffs between speed and quality of codebook/generation algorithms and offers new ways to produce excellent codebooks with only modest computation cost. It compares the performance of four algorithms for constructing codebooks. The LBG method of Linde, Buzo, and Gray (1980) produces the best codebooks but requires the most computation. The method by Equitz (1987, 1989) produces codebooks nearly as good and requires somewhat less computation. It describes a new method based on eigenvector subdivision that produces useable codebooks in a fraction of the computational effort of either of the other methods. A fourth hybrid method yields very good codebooks with modest computation by using the eigenvector subdivision method to obtain a first approximation that is refined with LBG optimization.<<ETX>>