Marshnil Vipin Dave

A Variation Tolerant Current-Mode Signaling Scheme for On-Chip Interconnects

Current-mode signaling (CMS) with dynamic overdriving is one of the most promising scheme for high-speed low-power communication over long on-chip interconnects. However, they are sensitive to parameter variations due to reduced voltage swings on the line. In this paper, we propose a variation tolerant dynamic overdriving CMS scheme. The proposed CMS scheme and a competing CMS scheme (CMS-Fb) are fabricated in 180-nm CMOS technology. Measurement results show that the proposed scheme offers 34% reduction in energy/bit and 42% reduction in energy-delay-product over CMS-Fb scheme for a 10 mm line operating at 0.64 Gbps of data rate. Simulations indicate that the proposed CMS scheme consumes 0.297 pJ/bit for data transfer over the 10 mm line at 2.63 Gb/s. Measurements indicate that the delay of CMS-Fb becomes 2.5 times its nominal value in the presence of intra-die variations whereas the delay of the proposed scheme changes by only 5% for the same amount of intra-die variations. Measurement and simulation results show that both the schemes are robust against inter-die variations. Experiments and simulations also indicate that the proposed CMS scheme is more robust against practical variations in supply and temperature as compared to CMS-Fb scheme.

A process variation tolerant, high-speed and low-power current mode signaling scheme for on-chip interconnects

Current mode signaling(CMS) scheme is one of the promising alternatives to voltage mode buffer insertion scheme for high-speed low-power data transmission over long on-chip interconnects. In this paper we present a CMS scheme with dynamic overdriving driver (DOD) whose performance is robust against intra-die and inter-die process variations. We show that throughput of the CMS scheme proposed in [1] degrades by 33% in the presence of intra-die process variations whereas that of the scheme in [2] degrades by 36% in the worst case process corner. Simulation results show that throughput of the proposed CMS scheme degrades by only 9.5% in presence of intra-die process variations and 22% in the worst case process corner. In this process corner, logic speed itself degrades by 23% and hence 22% of throughput degradation of the proposed signaling scheme is not a major concern. In the typical process corner, the proposed CMS scheme shows 14% and 19% improvement in delay and power, respectively over CMS scheme proposed in [1].

800-nA Process-and-Voltage-Invariant 106-dB PSRR PTAT Current Reference

This brief presents a novel process-and-voltage-invariant proportional to absolute temperature (PTAT) current reference. The proposed circuit is designed and fabricated in 180-nm mixed-mode CMOS technology. Measurement results show that the IPTAT varies only by ±2.4% (±3σ/mean) across 18 test chips. One thousand Monte Carlo simulation runs show that the maximum deviation (±3σ/mean) from the desired value of the PTAT current is ±5.4%. The proposed PTAT current reference uses a process, voltage, and temperature (PVT)-invariant resistor circuit having RON variation reduced by 4.2 times, as compared to a fixed biased MOSFET. The proposed PTAT current reference draws only 800-nA current from the supply voltage and also exhibits a high dc power supply rejection ratio (PSRR) of 106 dB. This brief also presents a PVT-invariant transconductance using the implemented PVT-invariant resistor.

A Low-Power Low-Skew Current-Mode Clock Distribution Network in 90nm CMOS Technology

A current-mode clock distribution network (CMCDN) for low-power low-skew on-chip clock distribution is presented in this paper. A novel low-power current-mode receiver circuit with common-mode correction for the CM-CDN is also presented. The CM-CDN and associated receiver circuit are designed and optimized in 90nm CMOS process with 1V supply voltage. The performance of the proposed CM-CDN is analyzed and simulated under parameter variations using corner analysis as well as Monte Carlo model files provided by the foundry. It is shown that the worst case skew of a 1-Level H-Tree CM-CDN is 21ps considering on-chip process variation whereas skew of an optimized voltage-mode CDN (VM-CDN) in the same process is 33ps. Power consumption of the proposed CM-CDN operating at 4GHz is 6.28mW which is 57% less as compared to the voltage-mode CDN. Also for the same input impedance of 200O, the proposed receiver consumes a power of 521.4µW which is 35% less than that of state of the art current-mode receiver.

A process and temperature compensated current reference circuit in CMOS process

A novel current reference circuit that compensates for process and temperature variations without any extra trimming is proposed in this paper. Four thousand Monte Carlo simulations show that the maximum % error (deviation from the desired value) in the reference current is +/-5.07% considering process variations (die-to-die, wafer-to-wafer and batch-to-batch). Considering process variations and temperature change from 0^oC to 100^oC both, the maximum error in the reference current is+/-8.56%. The proposed circuit has been fabricated in 180nm CMOS process. Measurement results on 50 dice at room temperature show that the mean of the proposed reference current is 9.39% away from its designed value. Mean of drain current of a fixed biased MOSFET fabricated in the same run is 35.41% away from its designed value. Measurements at four different temperatures, 27^oC, 50^oC, 75^oC and 100^oC, on these dice show that the maximum error in the reference current is 17% whereas that in the drain current of a fixed biased MOSFET is 126%. In other words, the proposed current reference circuit reduces the maximum error by a factor of 7 (from 126% to 17%) when process and temperature variations both are considered without trimming. With a simple trimming circuit the maximum variation in the reference current is reduced to +/-3.17%

Low-power current-mode transceiver for on-chip bidirectional buses

This paper presents a current-mode signalling scheme for bidirectional long on-chip interconnects. The transceiver has been fabricated in 180nm CMOS process. Features of the proposed scheme are driver pre-emphasis and low-impedance termination. While no extra repeater is needed for line lengths up to 8mm long the scheme improves the delay by 34% for 2mm-8mm long lines, compared to bidirectional voltage-mode links. The scheme also improves the power performance for line lengths longer than 2mm, operating at data rates higher than 180Mbps. Measurement results show that delay and power-delay product improve by 18% and 3.7×, respectively, compared to simulation results of the voltage-mode scheme.

Low power current mode receiver with inductive input impedance

In this paper we show that current mode signaling system with receivers using inductive input impedance can provide a low power solution to high speed data transmission over long lines. We show that beta multiplier circuits can be designed such that they exhibit inductive input impedance and their use as current mode receivers provides significant enhancement in data rates. Simulation results show that it is possible to transmit data at eight times higher data rates than voltage mode with an one order of magnitude lower power consumption. Even compared to other current mode signaling systems, those using receiver with inductive input impedance show around 50% improvement in data rate at marginally lower power consumption.

A Feed-Forward Equalizer for Capacitively Coupled On-Chip Interconnect

Repeaterless low swing interconnects are potential candidates for high speed low power signaling over on-chip global wires. Capacitive pre-emphasis at the transmitter has been shown to improve the achievable data rate by increasing the relative power at high frequencies. This paper shows an improved transmitter with a 1-tap feed-forward equalizer in addition to capacitive pre-emphasis. A design method for finding the transmitter design parameters using scrupulously chosen bit vectors is also presented. Post layout simulations show that the proposed link achieves a data rate of 4 Gbps over a 10 mm long M8 line with energy consumption of 313 fJ/bit in 90 nm CMOS technology.

Energy efficient current-mode signaling scheme

This paper describes a novel energy-efficient current-mode signaling scheme (CMS scheme) for long on-chip interconnects. The scheme was fabricated in 180nm process. Measurement results show that the proposed 6mm long link offers 22% improvement in delay with 81% lower energy consumption at 0.62Gbps over the voltage-mode scheme. The proposed scheme offers 20% improvement in power-delay-product over the CMS scheme proposed by Katoch et al. in [5]. Furthermore, it is less sensitive to intra-die variations.

A Fully On-Chip PT-Invariant Transconductor

This brief presents a novel process and temperature (PT)-invariant transconductor, fabricated and tested in 180-nm CMOS technology. It uses a novel bias circuit for implementing a PT-invariant transconductor using a MOSFET in triode region. Measurements show that the transconductance varies only by ±3.4% across 18 fabricated chips and over temperatures ranging from 25 °C to 100 °C. Simulations show that variation of the transconductance across process corners is ±6.7% and across temperature range of 0 °C to 100 °C is ±1.6%. The proposed PT-invariant transconductor has the minimum variation among the fully on-chip transconductors reported so far. The proposed circuit consumes 136 μW of power.