Maryam Shojaei Baghini

Sub-20 nm gate length FinFET design: Can high-κ spacers make a difference?

Sub-20 nm gate length FinFETs, are constrained by the very thin fin thickness (TFIN) necessary to maintain acceptable short-channel performance. For the 45 nm technology node and below, a novel device design methodology for undoped underlapped FinFETs with high-kappa spacers is presented to achieve higher circuit speed and SRAM cells with higher stability, lower leakage, faster access times and higher robustness to process variations compared to overlapped FinFETs. While comparing different FinFETs, we propose ON-current per fin as the parameter to be optimized instead of ON-current normalized to electrical width.

RF energy harvesting system from cell towers in 900MHz band

An experimental RF energy harvesting system to harvest energy from cell towers is presented in this paper. An electromagnetically-coupled square microstrip antenna is designed and fabricated for deployment in the presented system. Antenna gain of 9.1dB and bandwidth from 877 MHz to 998 MHz is achieved. A Schottky diode-based single stage voltage doubler and six-stage voltage doubler has also been designed and fabricated for DC voltage generation. Measured results show that a voltage of 2.78V is obtained at a distance of 10m from the cell tower and a voltage of 0.87V is obtained at a distance of 50m.

Part I: Mixed-Signal Performance of Various High-Voltage Drain-Extended MOS Devices

In this paper, the optimization issues of various drain-extended devices are discussed for input/output applications. The mixed-signal performance, impact of process variations, and gate oxide reliability of these devices are compared. Lightly doped drain MOS (LDDMOS) was found to have a moderate performance advantage as compared to shallow trench isolation (STI) and non-STI drain-extended MOS (DeMOS) devices. Non-STI DeMOS devices have improved circuit performance but suffer from the worst gate oxide reliability. Incorporating an STI region underneath the gate-drain overlap improves the gate oxide reliability, although it degrades the mixed-signal characteristics of the device. The single-halo nature of DeMOS devices has been shown to be effective in suppressing the short-channel effects.

A Variation Tolerant Current-Mode Signaling Scheme for On-Chip Interconnects

Current-mode signaling (CMS) with dynamic overdriving is one of the most promising scheme for high-speed low-power communication over long on-chip interconnects. However, they are sensitive to parameter variations due to reduced voltage swings on the line. In this paper, we propose a variation tolerant dynamic overdriving CMS scheme. The proposed CMS scheme and a competing CMS scheme (CMS-Fb) are fabricated in 180-nm CMOS technology. Measurement results show that the proposed scheme offers 34% reduction in energy/bit and 42% reduction in energy-delay-product over CMS-Fb scheme for a 10 mm line operating at 0.64 Gbps of data rate. Simulations indicate that the proposed CMS scheme consumes 0.297 pJ/bit for data transfer over the 10 mm line at 2.63 Gb/s. Measurements indicate that the delay of CMS-Fb becomes 2.5 times its nominal value in the presence of intra-die variations whereas the delay of the proposed scheme changes by only 5% for the same amount of intra-die variations. Measurement and simulation results show that both the schemes are robust against inter-die variations. Experiments and simulations also indicate that the proposed CMS scheme is more robust against practical variations in supply and temperature as compared to CMS-Fb scheme.

A Novel and Robust Approach for Common Mode Feedback Using IDDG FinFET

In this paper, we propose a novel and robust approach for common mode feedback (CMFB) for a differential amplifier using independently driven double gate (IDDG) FinFET technology. The performance of a differential amplifier with and without the proposed CMFB scheme is compared using 2-D mixed mode device and circuit simulations. It is shown from extensive simulation results that it is possible to achieve a common mode rejection ratio of 90 dB with improved performance in terms of area, power, and bandwidth even in the presence of process variations. Stability analysis shows that the proposed CMFB scheme does not need any compensating network. The idea is validated using extensive mixed-mode circuit simulations on IDDG FinFET circuits in sub-45-nm node technologies.

Toward System on Chip (SoC) Development Using FinFET Technology: Challenges, Solutions, Process Co-Development & Optimization Guidelines

In this paper, the impact of process/technology co-optimization on System-on-Chip (SoC) performance using detailed 3-D process/device simulations has been studied for nanoscale FinFET devices. We investigated challenges in FinFET device optimization and scaling while using standard ion implantation process for both overlap and underlap designs. Moreover, an implant-free (IF) complementary metal-oxide-semiconductor process is discussed for better scalability with improved performance. FinFETs designed using this IF process shows a ~2× improvement in static random-access memory and digital input/ output performance. Additionally, a modification to the IF process is proposed, which further helps in achieving an improved logic and analog performance for overall SoC development.

A Novel Bottom Spacer FinFET Structure for Improved Short-Channel, Power-Delay, and Thermal Performance

For the first time, we propose a novel bottom spacer fin-shaped field-effect-transistor (FinFET) structure for logic applications suitable for system-on-chip (SoC) requirements. The proposed device achieved improved short-channel, power-delay, and self-heating performance compared with standard silicon-on-insulator FinFETs. Process aspects of the proposed device are also discussed in this paper. Physical insight into the improvement toward the short-channel performance and power dissipation is given through a detailed 3-D device/mixed-mode simulation. The self-heating behavior of the proposed device is compared with standard FinFETs by using detailed electrothermal simulations. The proposed device requires an extra process step but enables smaller electrical width for self-loaded circuits and is an excellent option for SoC applications.

Broadband Bent Triangular Omnidirectional Antenna for RF Energy Harvesting

In this letter, a broadband bent triangular omnidirectional antenna is presented for RF energy harvesting. The antenna has a bandwidth for VSWR ≤ 2 from 850 MHz to 1.94 GHz. The antenna is designed to receive both horizontal and vertical polarized waves and has a stable radiation pattern over the entire bandwidth. Antenna has also been optimized for energy harvesting application and it is designed for 100 Ω input impedance to provide a passive voltage amplification and impedance matching to the rectifier. A peak efficiency of 60% and 17% is obtained for a load of 500 Ω at 980 and 1800 MHz, respectively. At a cell site while harvesting all bands simultaneously a voltage of 3.76 V for open circuit and 1.38 V across a load of 4.3 k Ω is obtained at a distance of 25 m using an array of two elements of the rectenna.

Differential Microstrip Antenna for RF Energy Harvesting

A differential microstrip antenna with improved gain for RF energy harvesting is presented in this paper. The developed antenna can be used in either center grounded or differential configuration. The antenna is designed and fabricated for GSM900 band (890-960 MHz). The antenna has a gain of 8.5 dBi at the center frequency and exhibits VSWR ≤ 2 for frequencies between 870 MHz to 1.05 GHz. The efficiency of the antenna is 80%. The developed antenna finds its application in energy harvesting, RFID tags and in wireless communication circuits, where differential inputs/outputs are needed. A complete differential RF energy harvesting system with a peak efficiency of 65.3% for a load of 3 kΩ is also developed.

Impact of Technology Scaling on Metastability Performance of CMOS Synchronizing Latches

In this paper, we use circuit simulations to characterize the effects of technology scaling on the metastability parameters of CMOS latches used as synchronizers. We perform this characterization by obtaining a synchronization error probability curve from a histogram of the latch delay. The main metastability parameters of CMOS latches are /spl tau//sub m/ and T/sub w/. /spl tau//sub m/ is the exponential time constant of the rate of decay of metastability and T/sub w/ is effective metastability window size at a normal propagation delay. Both parameters can be extracted from a histogram of the latch delay. This paper also explains a way to calibrate the simulator for accuracy. The simulations indicate that /spl tau//sub m/ scales better than the technology scale factor. T/sub w/ also scales down but its factor cannot be estimated as well as that of /spl tau//sub m/. This is because T/sub w/ is a complex function of signal and clock edge rate and logic threshold level.