Martin Bolton

Parallel controller synthesis for programmable logic devices

Abstract The standard approach to parallel controller design uses sequential controller design techniques. However, since these techniques cannot represent concurrent states, the problem must first be partitioned and then designed as a number of linked finite state machines. This initial partitioning is usually non-optimum and limits the amount of concurrency in the subsequent design, where the interaction between the finite state machines also makes verification difficult. This paper presents an alternative technique for parallel controller design in which a synchronous, interpreted Petri net is used to model the controllers specification as a single parallel network. No pre-partitioning is necessary, and the amount of concurrency dynamically reflects the amount of parallel activity on the data path. The formalism provided by the technique also reduces the likelihood of parallel synchronization errors. The technique is illustrated with the design of a parallel controller for a transputer link adapter and its implementation on a programmable logic device.

Self-clocked asynchronous state machine design with PAL22IP6

Abstract The standard methods for design of asynchronous sequential machines are usually complicated due to critical races and hazards, and necessitate special state assignment techniques often leading to extra hardware. The paper presents a systematic method which can be implemented using a recently introduced PAL device, the 221P6, without having to consider critical races and hazards. State assignments can be arbitrary and minimal. State machines of up to 64 states can be accommodated in a single chip. The method is applied to the design of a VMEbus requester, and the use of CAD packages to develop and simulate such designs is discussed.