Marian Adamski

The application of reconfigurable logic to controller design

Abstract This paper presents a framework that performs the programmable logic synthesis of rule-based descriptions of concurrent controllers. These descriptions can be obtained from several specification models of those controllers (for example, Control Interpreted Petri net, Grafcet or the IEC 1131-3 Sequential Function Chart). The internal description, in the form of symbolic conditional decision rules, is then transformed into a format that is accepted by standard FPLD and FPGA simulators and synthesisers, for example OrCAD or VHDL. The concurrent state machine model of the logic controller is verified using the well-developed Petri-net theory, and then it is translated through automated processes into a selected FPGA specification format, for example the Xilinx netlist format (XNF). This paper presents part of a broad project in the field of hardware/software co-design. The main purpose is to develop different implementations of controllers using a simple, standard and well-known design methodology like SFC (Grafcet) or Petri nets. The paper deals exclusively with the design of FPGA-based controllers.

From interpreted Petri net specification to reprogrammable logic controller design

The goal of this paper is to present the design methodology for the modelling and synthesis of discrete event controllers for compact, fast and reliable embedded systems, using related Petri net theory, rule-based system theory (conditional mathematical logic), and hardware description languages (VHDL, Verilog). The well structured specification, which is represented in the human readable logic language, has a direct impact on the validation, formal verification and implementation of application specific logic controllers (ASLC) mapped into reconfigurable logic devices (FPGA). Reprogrammable logic controllers (RLC) may replace traditional PLCs in many industrial applications.

Hardware Behavioural Modelling, Verification and Synthesis with UML 2.x Activity Diagrams

Modelling of hardware behavior is the fundamental process of hardware design project. Possible specification techniques, like UML 2.x Activity Diagrams or Control Interpreted Petri Nets, all have its advantages and disadvantages. Combing the accessibility of UML and full support for formal verification of Petri nets may significantly improve design quality. The article propose a system supporting logic controllers development, starting from a specification, going through formal verification (including model checking), and ending with synthesis.

Application of comparability graphs in decomposition of Petri nets

In the article we present a new algorithm of Petri net decomposition into State Machine Components (SMCs). The idea bases on the application of the comparability graph theory. The comparability graphs are classified as a subclass of the perfect graphs and have unique properties. If a graph belongs to the comparability class, many problems (like graph coloring, maximal clique problem) can be solved in polynomial time. Therefore, if the sequentiality graph of a Petri net belongs to comparability class, the whole decomposition process turns to be polynomial. The preliminary experiments have demonstrated the effectiveness of the proposed idea. Over 90% of concurrency and sequentiality graphs of tested benchmarks belong to the comparability class. The efficiency is even higher if the Petri net class is reduced to the EFC (Extended Free-Choice).

Model Checking of UML Activity Diagrams in Logic Controllers Design

The article presents a novel approach to model checking of UML activity diagrams (in version 2.x) for logic controller specification. A novel idea to design embedded systems by means of activity diagrams is introduced, using the previously proposed rule-based logical model suitable both for formal verification and logic synthesis. As the result implemented solution is consistent with the verified specification delivered in form of an user-friendly UML activity diagram. The idea is presented on a simple control process of two vehicles movement. Model checking technique is used to verify system model against behavioral properties expressed in temporal logic. In case of detected errors appropriate counterexamples are generated.

FORMAL REASONING IN LOGIC DESIGN OF RECONFIGURABLE CONTROLLERS

The rigorous digital design of embedded Reconfigurable Logic Controller starts from hierarchical concurrent state machine model (HCSM), which has been formally derived from modular control interpreted Petri net. The colored tokens, arcs, places and transitions distinguish nested State Machine Modules. Colored coordination places, called doubles facilitate effective and flexible Petri net state encoding. The rule based on a textual logic description of the Petri net is accepted by the hardware description language VHDL and easily mapped into Field Programmable Gate Array macrocells. Several combinatorial procedures in formal digital design of logic controller are supported by formal reasoning in the monotone Gentzen calculus.

Application of Hypergraphs to SMCs Selection

The paper deals with selection of State Machine Components (SMCs) based on Hypergraphs theory. The entire selection process use Petri nets as benchmarks. As it is known, Petri nets are used for modeling of concurrency processes. The SMCs selection problem is classified as NP-Hard which means there does not exist polynomial algorithm which provides an exact solution. In the article we show three SMCs selection methods, advantages and disadvantages of each, results of comparison between traditional methods (exponential backtracking, polynomial greedy) and an exact transversal method based on hypergraphs theory, their efficiency and propriety. An exact transversal method allows to obtain exact solution in polynomial time if selection hypergraph belongs to xt-hypergraph class.

UML state machine implementation in FPGA devices by means of dual model and Verilog

The paper presents the methodology of the logic controller development process based on the UML state machine diagram. The development process covers the logic synthesis and the implementation by means of the intermediate model based on Petri net formalism. The transformation between these two formal models is performed at the metamodels level according to the Model Driven Architecture (MDA). Semantics of the hierarchical configurable Petri net (HCfgPN) was adopted for the preemption and resumption mechanism. Operational subnet of HCfgPN model may be verified using formal methods.

Synthesis of Petri nets into FPGA with operation flexible memories

In this paper a new method of Petri net array-based synthesis is proposed. The method is based on the structured encoding of places by means of using minimal numbers of bits together with parallel decomposition of a digital system. State machine subnets, which are determined by colors are attached to places and transitions. Colored microoperations which are assigned to places are written into distributed and flexible memory. It leads to realization of a logic circuit in a two-level concurrent structure, where the combinational circuit of the first level is responsible for firing transitions, and the second level memories are used for generation of microoperations. Such an approach allows balanced usage of different kinds of resources available in modern FPGAs.

Application of an Exact Transversal Hypergraph in Selection of SM-Components

The paper deals with the application of the hypergraph theory in selection of State Machine Components (SM-Components) of Petri nets [1,2].As it is known, Petri nets are widely used for modeling of concurrency processes. However, in order to implement the concurrent automaton, an initial Petri net ought to be decomposed into sequential automata (SM-Components), which can be easily designed as an Finite-State-Machine (FSM) or Microprogrammed Controller [3]. The last step of the decomposition process of the Petri nets is selection of SM-Components. This stage is especially important because it determines the final number of sequential automata. In the article we propose a new idea of SM-Components selection. The aim of the method is reduction of the computational complexity from exponential to polynomial. Such a reduction can be done if the selection hypergraph belongs to the exact transversal hypergraphs (xt-hypergraphs) class. Since the recognition and generation of the first transversal in the xt-hypergraphs are both polynomial, the complete selection process can be performed in polynomial time. The proposed ideas are an extension of the concept presented in [1].The proposed method has been verified experimentally. The conducted investigations have shown that for more than 85% of examined Petri nets the selection process can be done via xt-hypergraphs.