Martin Flatscher

A Bulk Acoustic Wave (BAW) Based Transceiver for an In-Tire-Pressure Monitoring Sensor Node

Attaching a tire pressure monitoring system (TPMS) on the inner liner of a tire allows sensing of important additional technical parameters, such as vehicle load or tire wearout. The maximum weight of the sensor is limited to 5 grams including package, power supply, and antenna. Robustness is required against extreme levels of acceleration. The node size is limited to about 1 cm3 to avoid high force-gradients due to device-deformation and finally, a long power supply lifetime must be achieved. In this paper a low-power FSK transceiver is presented. Exploiting BAW resonators the use of a bulky and shock-sensitive crystal and a PLL can be avoided. This makes the system more robust and radically reduces the start-up time to 2 ¿s from few ms as in state-of-the-art crystal oscillator based systems. The current consumption of the transceiver is 6 mA in transmit mode with a transmit output power of 1 dBm and 8 mA in receive mode with a sensitivity of -90 dBm at a data rate of 50 kBit/s and a bit error rate of 10-2. The transceiver ASIC and a microcontroller ASIC, a MEMS sensor, and a BAW die are arranged in a 3-D chip stack for best compactness, lowest volume, and highest robustness. The sensor node allows sensing of pressure, acceleration, supply voltage and temperature.

A robust wireless sensor node for in-tire-pressure monitoring

State-of-the-art tire pressure monitoring systems (TPMS) are wireless sensor nodes mounted on the rim. Attaching the node on the inner liner of a tire allows sensing of additional technical parameters, such as road condition, tire wearout, temperature, tire friction, side slip, wheel speed, and vehicle load. They may be used for improved tracking and engine control, feedback to the power train and car-to-car communication purposes.

A power management unit for ultra-low power wireless sensor networks

Wireless sensor networks become more and more attractive due to their ongoing miniaturization and decreasing costs. One of the major challenges concerning the design is the power consumption of the wireless sensor node. Low power consumption is mandatory to guarantee a long lifetime if a battery is used as a power source or to allow the use of an energy harvester. In this work a multi-stage power management for a wireless sensor node is presented. Energy-efficient power management is achieved by employing several state machines controlling different power domains which can be turned on and off separately depending on the operating mode of the wireless sensor node. A test chip has been produced in an Infineon 130nm CMOS process. The presented wireless sensor node consumes 240 nA in power down mode, most of which is leakage current. In different deep-sleep modes it consumes between 750 nA and 1.5 µA.

A bulk acoustic wave(BAW)-based sensor node for automotive wireless sensor networks

SummaryThe following paper presents a 2.1 GHz transceiver, which makes use of BAW resonators to replace the external quartz crystal and the external band select filter. It has been fabricated in a 130 nm CMOS process and has a power consumption of 5 mA. To derive the specifications for the transceiver the requirements of a TPMS have been taken into consideration.ZusammenfassungDer folgende Artikel stellt einen 2,1-GHz-Transceiver vor, der anstelle einer externen Quarzreferenz und eines externen Hochfrequenzfilters BAW-Resonatoren einsetzt. Der Chip wurde in einem 130-nm-CMOS-Prozess gefertigt und hat einen Stromverbrauch von 5 mA. Um die Spezifikationen abzuleiten, wurden die Anforderungen an ein TPMS (Reifendrucküberwachungssystem) betrachtet.

A low noise amplifier with on-chip matching network and integrated bulk Acoustic Wave resonators for high image rejection

This paper presents a 2.45 GHz low noise amplifier (LNA), built in a 0.13 µm CMOS process. It has an on-chip matching network and contains integrated bulk acoustic wave (BAW) resonators for narrow-band filtering at RF. The voltage gain of LNA and matching network is 31.5 dB with 4.7 dB noise figure (NF) at a current consumption of 2 mA.

Asynchronous logic application in a power management unit for ultra low power wireless sensor nodes

This work presents the application of asynchronous logic style to control circuits of the on-chip power management unit (PMU) in a wireless sensor node. Because of the inherent property of asynchronous logic - to operate without any synchronous clock signal - it is the first choice circuit class for controllers in a clock-less environment. Due to the nature of the asynchronous logic, as it is to work in sensitivity to asynchronous input-changes without being separated by clock edges, the construction of such an asynchronous finite state machine (AFSM) requires careful synthesis and implementation methodology. The asynchronous circuit is realized by means of thick gate oxide transistors and it is directly connected to the power supply. Hence, no voltage regulator and no bandgap are required for the operation of the low power asynchronous circuit. The power management unit itself is applied in the architecture of an ultra low power sensor node circuit. Such circuits are supplied by a limited battery voltage or by an energy harvester and require low power architectures in order to deliver long operating times, especially during the power-down phase of the full circuit. The transceiver is manufactured in a 130 nm CMOS process and has to operate between −40 and 125°C.

Two on-chip bandwidth calibration methods for phase-locked loops used in wireless transceiver applications

Phase-locked loops (PLL) are essential building blocks in wireless transceivers. Concerning data transmission and reception the performance of the PLL is crucial for the overall performance of the whole system. The transmitter architecture of the presented system does not use mixers but the PLL itself for FSK modulation. Therefore especially the bandwidth of the PLL influences performance parameters. As the PLL bandwidth is subject to significant variations due to process, temperature and supply voltage, bandwidth calibration is an important measure to ensure the PLL performance specifications. This paper presents two methods which use building blocks of an existing transceiver to calibrate the PLL bandwidth. Both methods use existing features of the transceiver architecture and therefore require only minimal adjustments and in principal no additional building blocks in order to accomplish bandwidth calibration. The first method uses an ADC to measure the PLL Loop Filter Voltage and the second employs the receiver to observe the frequency and phase of the PLL output signal. The proposed methods have been verified by measurements using a test chip implemented in a low-cost Infineon 130 nm CMOS process and an FPGA board. The variation of the PLL bandwidth after calibration is lower than ±10% compared to more than ±60% for an uncalibrated PLL. The time needed for calibration lies between 32 μs and 200 μs.

Design of a digitally controlled oscillator for a Delta-Sigma phase-locked loop in a 0.13 µm CMOS-process

ZusammenfassungIn diesem Artikel werden drei verschiedene Oszillatortopologien untersucht. Der Oszillator soll in einer vollständig digitalen Phase-Locked Loop eingesetzt werden, die zur Frequenzsynthese für die lizenzfreien ISM/SRD-Frequenzbänder bei 315,0 MHz, 433,9 MHz und 868,3 MHz verwendet wird. Der Frequenzbereich liegt zwischen 75 MHz und 80 MHz und soll mittels eines digitalen Codewortes einstellbar sein.SummaryIn this paper three different oscillator topologies are investigated. The oscillator is to be used in an all-digital phase-locked loop for frequency synthesis for the ISM/SRD license-free frequency bands at 315.0 MHz, 433.9 MHz and 868.3 MHz. The oscillators frequency range is 75 MHz to 80 MHz and its frequency is controlled via a digital code word.

Investigation of two-point modulation to increase the GFSK data rate of PLL-based wireless transceivers of wireless sensor nodes

Gaussian Frequency-shift-keying (GFSK) is a widely used modulation scheme in state-of-the-art wireless transceivers. Most often a phase-locked-loop (PLL) is utilized for carrier generation and GFSK modulation. Using this architecture the maximum applicable data rate is limited by the PLLs bandwidth. This paper investigates the possibility of using two-point modulation in order to be able to choose the GFSK data rate independently of the bandwidth. The most important aspect of two-point modulation is the mismatch of the gain of the two modulation paths. Two methods which allow close gain matching are presented in this work. Time-domain simulations using Verilog-A models of the analog and RTL models of the digital building blocks of a wireless transceiver have been carried out and confirm the capability of extending its GFSK data rate to 1Mbps while using a PLL closed-loop bandwidth of 44.5 kHz.

Image rejection in a receiver frontend by means of BAW resonators and an image-reject architecture

ZusammenfassungDer Artikel beschreibt zwei Maßnahmen zur Unterdrückung der Spiegelfrequenz in einem 2,45-GHz-Empfänger. Der vorgestellte Empfänger ist Teil eines BAW-basierten Transceivers in einem reinen 130-nm-CMOS-Prozess. Sowohl die schmale Bandbreite von einzelnen BAW-Resonatoren wird zur Filterung im RF-Bereich verwendet als auch eine Image-Reject-Architektur zur zusätzlichen Unterdrückung der Spiegelfrequenz.SummaryThis paper describes two measures for image rejection in a 2.45 GHz receiver frontend. The presented receiver frontend is part of a BAW-based transceiver in a 130 nm pure CMOS process. It uses the narrow bandwidth of single BAW resonators for filtering at RF as well as an image-reject architecture for additional image suppression.