Jakob Jongsma

Two on-chip bandwidth calibration methods for phase-locked loops used in wireless transceiver applications

Phase-locked loops (PLL) are essential building blocks in wireless transceivers. Concerning data transmission and reception the performance of the PLL is crucial for the overall performance of the whole system. The transmitter architecture of the presented system does not use mixers but the PLL itself for FSK modulation. Therefore especially the bandwidth of the PLL influences performance parameters. As the PLL bandwidth is subject to significant variations due to process, temperature and supply voltage, bandwidth calibration is an important measure to ensure the PLL performance specifications. This paper presents two methods which use building blocks of an existing transceiver to calibrate the PLL bandwidth. Both methods use existing features of the transceiver architecture and therefore require only minimal adjustments and in principal no additional building blocks in order to accomplish bandwidth calibration. The first method uses an ADC to measure the PLL Loop Filter Voltage and the second employs the receiver to observe the frequency and phase of the PLL output signal. The proposed methods have been verified by measurements using a test chip implemented in a low-cost Infineon 130 nm CMOS process and an FPGA board. The variation of the PLL bandwidth after calibration is lower than ±10% compared to more than ±60% for an uncalibrated PLL. The time needed for calibration lies between 32 μs and 200 μs.

Design of a digitally controlled oscillator for a Delta-Sigma phase-locked loop in a 0.13 µm CMOS-process

ZusammenfassungIn diesem Artikel werden drei verschiedene Oszillatortopologien untersucht. Der Oszillator soll in einer vollständig digitalen Phase-Locked Loop eingesetzt werden, die zur Frequenzsynthese für die lizenzfreien ISM/SRD-Frequenzbänder bei 315,0 MHz, 433,9 MHz und 868,3 MHz verwendet wird. Der Frequenzbereich liegt zwischen 75 MHz und 80 MHz und soll mittels eines digitalen Codewortes einstellbar sein.SummaryIn this paper three different oscillator topologies are investigated. The oscillator is to be used in an all-digital phase-locked loop for frequency synthesis for the ISM/SRD license-free frequency bands at 315.0 MHz, 433.9 MHz and 868.3 MHz. The oscillators frequency range is 75 MHz to 80 MHz and its frequency is controlled via a digital code word.