Martin Kumm

An FPGA-Based Linear All-Digital Phase-Locked Loop

In this paper, an all-digital phase-locked loop (ADPLL) is presented, and it is implemented on a field-programmable gate array. All components like the phase detector (PD), oscillator, and loop filter are realized as digital discrete-time components fed from analog-to-digital converters. The phase detection is realized by generating first an analytic signal using a compact implementation of the Hilbert transform and then computing the instantaneous phase with the CORDIC algorithm. A phase-unwrap component was realized, which extends the linear range of the PD, so that the linear model is valid in the full frequency range. This property leads to a constant lock-in time for arbitrary frequency changes. An analytic solution for the lock-in frequency range and the stability range including processing delays is given. All relations to design an ADPLL of the presented structure are derived. A detailed example application of an ADPLL designed as an offset local oscillator is given.

A Digital Beam-Phase Control System for Heavy-Ion Synchrotrons

A closed-loop control system for damping undesired longitudinal oscillations of particle bunches in heavy-ion synchrotrons is presented. The system is based on technologies like digital signal processors (DSPs), modern field programmable gate arrays (FPGAs), and direct digital synthesis (DDS). After describing the technological challenges, the design of the system is presented, and some theoretical background is given. Finally, measurement results are presented which are in good agreement with simulations and theoretical predictions.

Pipelined adder graph optimization for high speed multiple constant multiplication

This paper addresses the direct optimization of pipelined adder graphs (PAGs) for high speed multiple constant multiplication (MCM). The optimization opportunities are described and a definition of the pipelined multiple constant multiplication (PMCM) problem is given. It is shown that the PMCM problem is a generalization of the MCM problem with limited adder depth (AD). A novel algorithm to solve the PMCM problem heuristically, called RPAG, is presented. RPAG outperforms previous methods which are based on pipelining the solutions of conventional MCM algorithms. A flexible cost evaluation is used which enables the optimization for FPGA or ASIC targets on high or low abstraction levels. Results for both technologies are given and compared with the most recent methods. Even for the special case of limited AD it is shown that RPAG often produces better results compared to the prominent Hcub algorithm with minimal total AD constraint.

Optimization of high speed pipelining in FPGA-based FIR filter design using genetic algorithm

This paper compares FPGA-based full pipelined multiplierless FIR filter design options. Comparison of Distributed Arithmetic (DA), Common Sub-Expression (CSE) sharing and n-dimensional Reduced Adder Graph (RAG-n) multiplierless filter design methods in term of size, speed, and A*T product are provided. Since DA designs are table-based and CSE/RAG-n designs are adder-based, FPGA synthesis design data are used for a realistic comparison. Superior results of a genetic algorithm based optimization of pipeline registers and non-output fundamental coefficients are shown. FIR filters (posted as open source by Kastner et al.) for filters in the length from 6 to 151 coefficients are used.

High speed low complexity FPGA-based FIR filters using pipelined adder graphs

A method for generating high speed FIR filters with low complexity for FPGAs is presented. The realization is split into two parts. First, an adder graph is obtained using an existing multiple constant multiplication (MCM) algorithm. This adder graph describes the required multiplier block of the FIR filter using only additions/subtractions and shifts. Secondly, a novel FPGA-specific combined schedule and pipeline optimization is performed to gain the maximum speed while using a minimal performance penalty. FPGA-specific characteristics are exploited during optimization including the reduction of pipeline registers by duplicating adders in later stages. The optimization is formulated as binary integer linear programming (BILP) problem. It is shown that the generated number of pipelined operations based on the Hcub MCM algorithm is reduced up to 29.1% on average compared to an as-soon-as-possible (ASAP) scheduling using cut-set retiming. Synthesis results are obtained by generating VHDL code, showing that the proposed method outperforms the recently proposed Add/Shift method in resource complexity (54.1% reduction on average) while a competitive performance is achieved (88.2% speed of Add/Shift on average).

Pipelined compressor tree optimization using integer linear programming

Compressor trees offer an effective realization of the multiple input addition needed by many arithmetic operations. However, mapping the commonly used carry save adders (CSA) of classical compressor trees to FPGAs suffers from a poor resource utilization. This can be enhanced by using generalized performance counters (GPCs). Prior work has shown that high efficient GPCs can be constructed by exploiting the low-level structure of the FPGA. However, due to their irregular shape, the selection of those is not straight forward. Furthermore, the compressor tree has to be pipelined to achieve the potential FPGA performance. Then, a selection between registered GPCs or flip-flops has to be done to balance the pipeline. This work defines the pipelined compressor tree synthesis as an optimization problem and proposes a (resource) optimal method using integer linear programming (ILP). Besides that, two new GPC mappings with high efficiency are proposed for Xilinx FPGAs.

Dynamically reconfigurable FIR filter architectures with fast reconfiguration

This work compares two finite impulse response (FIR) filter architectures for FPGAs for which the coefficients can be reconfigured during run-time. One is a recently proposed filter architecture based on distributed arithmetic (DA) and the other is based on a LUT multiplication scheme. Instead of using the common internal configuration access port (ICAP) for reconfiguration which is able to change the logic as well as the routing, it is sufficient to reconfigure only the logic in the regarded architectures. This is realized by using the configurable look-up table (CFGLUT) primitive of Xilinx that allows reconfiguration times which are orders of magnitudes faster than using ICAP. The resulting FIR filter architectures achieves reconfiguration times of typically less than 100 ns. They can be reconfigured with arbitrary coefficients that are only limited by their length and word size. As their resource consumptions depend on different parameters of the filter, a detailed comparison is done. It turned out that if the input word size is greater than approximately half the number of coefficients, the LUT based multiplication scheme needs less resources than the DA architecture and vice versa.

Reconfigurable FIR filter using distributed arithmetic on FPGAs

An architecture for a dynamically run-time reconfigurable finite impulse response (FIR) filter is presented in this work. It is based on distributed arithmetic (DA) combined with a look-up table (LUT) reduction technique which allows the direct mapping to reconfigurable LUTs (CFGLUT) of the latest Xilinx FPGAs. The resulting FIR filter can be reconfigured with arbitrary coefficients which are only limited by their length and word size. The number of filter instances for reconfiguration is only limited by the block memory of the FPGA which typically allows hundreds of different configurations. The proposed reconfigurable architecture consumes 16% less slices on average than a fixed coefficient DA filter generated by Xilinx Coregen. As the direct mapping to CFGLUTs leads to invalid filter output during reconfiguration, an alternative architecture is proposed which avoids this limitation at the cost of 19% more slice resources on average. Using a parallel reconfiguration scheme, reconfiguration times of about 100ns could be achieved.

Multiple constant multiplication with ternary adders

The scaling operation, i. e., the multiplication with a single constant is a frequently used operation in many kinds of numeric algorithms. The multiple constant multiplication (MCM) is a generalization where a variable is multiplied by several constants. This kind of operation is heavily used, e. g., in digital filters or discrete transforms. It was shown in recent work that small, fast and power efficient MCM implementations can be realized by using the fast carry chains of FPGAs rather than wasting specialized embedded multipliers. However, in the work so far, only common two-input adders were used. As FPGAs today support ternary adders, i. e., adders with three inputs, this work investigates the optimization of pipelined MCM circuits which include ternary adders. It is shown experimentally that 27% less operations are needed on average by using ternary adders, resulting in 15% slice (Xilinx) and 10% ALM (Altera) reductions, respectively.

Digital hilbert transformers for FPGA-based phase-locked loops

The phase detector is a main building block in phase-locked loop (PLL) applications. FPGAs permit the realtime implementation of the CORDIC algorithm which offers an efficient solution for an accurate phase detection, provided that the signal is available as an analytic signal. Different architectures for generating analytic signals by approximating the Hilbert transform were analyzed. Thereby, the focus has been on the demands based on the PLL application and the efficient implementation on FPGAs. Two methods were implemented using either FIR or complex filters. The FIR method results in a remaining phase error that has a zero mean value in time domain. An efficient IIR low-pass structure is proposed to suppress this phase error. The complex filters were implemented using a novel method based on complex, multiplier-less frequency sampling filters. Structures with different complexities are presented. A better result was achieved compared to a standard IIR filter design.