Peter Zipf

An FPGA-Based Linear All-Digital Phase-Locked Loop

In this paper, an all-digital phase-locked loop (ADPLL) is presented, and it is implemented on a field-programmable gate array. All components like the phase detector (PD), oscillator, and loop filter are realized as digital discrete-time components fed from analog-to-digital converters. The phase detection is realized by generating first an analytic signal using a compact implementation of the Hilbert transform and then computing the instantaneous phase with the CORDIC algorithm. A phase-unwrap component was realized, which extends the linear range of the PD, so that the linear model is valid in the full frequency range. This property leads to a constant lock-in time for arbitrary frequency changes. An analytic solution for the lock-in frequency range and the stability range including processing delays is given. All relations to design an ADPLL of the presented structure are derived. A detailed example application of an ADPLL designed as an offset local oscillator is given.

Towards a unique FPGA-based identification circuit using process variations

A compact chip identification (ID) circuit with improved reliability is presented. Ring oscillators are used to measure the spatial process variation and the ID is based on their relative speeds. A novel averaging and postprocessing scheme is employed to accurately determine the faster of two similar-frequency ring oscillators in the presence of noise. Using this scheme, the average number of unstable bits i.e. bits which can change in value between readings, measured on an FPGA is shown to be reduced from 5.3% to 0.9% at 20°C. Within the range 20 – 60°C, the percentage of unstable bits is within 2.8%. An analysis of the effectiveness of the scheme and the distribution of the errors is given over different temperature ranges and FPGA chips.

Pipelined adder graph optimization for high speed multiple constant multiplication

This paper addresses the direct optimization of pipelined adder graphs (PAGs) for high speed multiple constant multiplication (MCM). The optimization opportunities are described and a definition of the pipelined multiple constant multiplication (PMCM) problem is given. It is shown that the PMCM problem is a generalization of the MCM problem with limited adder depth (AD). A novel algorithm to solve the PMCM problem heuristically, called RPAG, is presented. RPAG outperforms previous methods which are based on pipelining the solutions of conventional MCM algorithms. A flexible cost evaluation is used which enables the optimization for FPGA or ASIC targets on high or low abstraction levels. Results for both technologies are given and compared with the most recent methods. Even for the special case of limited AD it is shown that RPAG often produces better results compared to the prominent Hcub algorithm with minimal total AD constraint.

Design Concepts for a Dynamically ReconfigurableWireless Sensor Node

Wireless sensor networks require the design of highly energy-efficient and yet flexible sensor nodes, which is very difficult to realize with classical architectures. In this paper we propose a new approach based on the tight coupling of a small processor with a dynamically reconfigurable function unit that is optimized for wireless sensor network applications. Dynamic reconfiguration is part of the regular operation mode and the key concept to achieve a small design that provides sufficient performance, high adaptivity and good energy-efficiency

High speed low complexity FPGA-based FIR filters using pipelined adder graphs

A method for generating high speed FIR filters with low complexity for FPGAs is presented. The realization is split into two parts. First, an adder graph is obtained using an existing multiple constant multiplication (MCM) algorithm. This adder graph describes the required multiplier block of the FIR filter using only additions/subtractions and shifts. Secondly, a novel FPGA-specific combined schedule and pipeline optimization is performed to gain the maximum speed while using a minimal performance penalty. FPGA-specific characteristics are exploited during optimization including the reduction of pipeline registers by duplicating adders in later stages. The optimization is formulated as binary integer linear programming (BILP) problem. It is shown that the generated number of pipelined operations based on the Hcub MCM algorithm is reduced up to 29.1% on average compared to an as-soon-as-possible (ASAP) scheduling using cut-set retiming. Synthesis results are obtained by generating VHDL code, showing that the proposed method outperforms the recently proposed Add/Shift method in resource complexity (54.1% reduction on average) while a competitive performance is achieved (88.2% speed of Add/Shift on average).

The XPP Architecture and Its Co-simulation Within the Simulink Environment

This paper offers an overview of the XPP, a coarse-grained reconfigurable architecture, and presents a solution for its integration into a Simulink design flow for rapid prototyping. This includes a system-level co-simulation followed by the automated code generation for an embedded target platform. In order to realize this functionality, a custom Simulink module has been developed. During the co-simulation phase, it acts as a wrapper for an external simulator, whereas when code is generated, it is responsible for generating the appropriate function calls for communicating with the XPP device. Of these two aspects, only the co-simulation is considered here.

A Domain-Specific Dynamically Reconfigurable Hardware Platform for Wireless Sensor Networks

In this paper, a new generic sensor node platform for wireless sensor networks (WSN) is presented, demonstrating that high energy efficiency, flexibility and performance can be achieved by the use of dynamically reconfigurable hardware in the WSN domain. The core of the presented platform is formed by the combination of a RISC processor and a dynamically reconfigurable function unit optimized for efficient data processing in WSN applications. A novel reconfiguration mechanism is applied enabling rapid dynamic reconfiguration with very short latencies. Thereby, we can show that the overhead on performance and energy consumption caused by dynamic reconfiguration can be reduced to a moderate, non-critical value and is clearly outweighed by the significantly improved performance and energy consumption for data processing on the reconfigurable function unit. The evaluation of the platform and its comparison to a standard processor-based platform finally demonstrate high gains in energy-efficiency of one to two orders of magnitude.

On the design of reconfigurable multipliers for integer and Galois field multiplication

Multiplication is a vital function for practically any DSP system. Some common DSP algorithms require different multiplication types, specifically integer or Galois Field (GF) multiplication. Since both functions share similarities in their structures, the potential is given for efficiently combining them in a single reconfigurable VLSI circuit, leading to competitive designs in terms of area, performance, and power consumption. This will be analysed and discussed in detail for 10 reconfigurable multiplier alternatives that are based on different strategies for the combination of integer and GF multiplication. Each result is compared to a reference architecture, showing area savings of up to 20% at a marginal increase in delay, and an increase in power consumption of 25% and above. This gives evidence that function-specific reconfigurable circuits can achieve considerable improvements in at least one design objective with only a moderate degradation in others. From this perspective, function-specific reconfigurable circuits can be considered feasible alternatives to standard ASIC solutions.

A decentralised task mapping approach for homogeneous multiprocessor network-on-chips

We present a heuristic algorithm for the run-time distribution of task sets in a homogeneous Multiprocessor network-on-chip. The algorithm is itself distributed over the processors and thus can be applied to systems of arbitrary size. Also, tasks added at run-time can be handled without any difficulty, allowing for inline optimisation. Based on local information on processor workload, task size, communication requirements, and link contention, iterative decisions on task migrations to other processors are made. The mapping results for several example task sets are first compared with those of an exact (enumeration) algorithm with global information for a 3×3 processor array. The results show that the mapping quality achieved by our distributed algorithm is within 25% of that of the exact algorithm. For larger array sizes, simulated annealing is used as a reference and the behaviour of our algorithm is investigated. The mapping quality of the algorithm can be shown to be within a reasonable range (below 30% mostly) of the reference. This adaptability and the low computation and communication overhead of the distributed heuristic clearly indicate that decentralised algorithms are a favourable solution for an automatic task distribution.

Pipelined compressor tree optimization using integer linear programming

Compressor trees offer an effective realization of the multiple input addition needed by many arithmetic operations. However, mapping the commonly used carry save adders (CSA) of classical compressor trees to FPGAs suffers from a poor resource utilization. This can be enhanced by using generalized performance counters (GPCs). Prior work has shown that high efficient GPCs can be constructed by exploiting the low-level structure of the FPGA. However, due to their irregular shape, the selection of those is not straight forward. Furthermore, the compressor tree has to be pipelined to achieve the potential FPGA performance. Then, a selection between registered GPCs or flip-flops has to be done to balance the pipeline. This work defines the pipelined compressor tree synthesis as an optimization problem and proposes a (resource) optimal method using integer linear programming (ILP). Besides that, two new GPC mappings with high efficiency are proposed for Xilinx FPGAs.