Martin Saint-Laurent

Cache Design for Low Power and High Yield

A novel circuit approach to increase SRAM static noise margin (SNM) and enable lower operating voltage is described. Increasing process variability [1] [2] for new technologies coupled with increased reliability effects like negative bias temperature instability (NBTI) [3] all contribute to raising the minimum voltage required for stable SRAM. Our strategy is to improve the noise margin of the 6T SRAM cell by reducing the effect of parametric variation of the cell [4], especially in the low voltage operation mode. This is done using a novel circuit that selectively reduces the voltage swing on the world line and reduces the memory supply voltage during write operation. The proposed design increases the SRAM static noise margin (SNM) and write margin using a single voltage supply and with minimum impact to chip area, complexity, and timing. The technique supports both on-chip corner identification to adapt the SRAM behavior to silicon, and software controllability to tradeoff yield, power, and performance.

10.1 A 28nm DSP powered by an on-chip LDO for high-performance and energy-efficient mobile applications

A very-long instruction word (VLIW) Hexagon™ DSP is fabricated using a 28 nm high-κ metal-gate process technology optimized for mobile applications [1]. The DSP is designed for a heterogeneous computing environment. It targets high performance and low power across a wide variety of multimedia and modem applications, under aggressive area targets. Its architecture pursues high IPC as opposed to high frequency [2]. It includes a 32 kB L1 data cache (D

A low-power clock gating cell optimized for low-voltage operation in a 45-nm technology

), a 16 kB L1 instruction cache (I

Energy efficient design techniques for a digital signal processor

), and a 256 kB L2 cache.

A 65-nm pulsed latch with a single clocked transistor

This paper discusses a novel clock gating cell (CGC) optimized for low-power and low-voltage operation. First, the limitations of the conventional CGC topology are analyzed and several improvements are proposed. Next, the new CGC topology is introduced and compared to the conventional one in terms of dynamic clock power, leakage, area, timing, and low-voltage operation. Finally, the paper discusses the silicon measurements taken to verify the correct functionality of the new circuit in a 45-nm technology optimized for low standby power.

Transistor-interconnect mobile system-on-chip co-design method for holistic battery energy minimization

Power is often cited as a key design metric for IC designs. However, for many integrated solutions a better measure of design quality is the overall energy efficiency of the design as low power does not always imply high energy efficiency. Many design tradeoffs must be made to balance the often-conflicting goals of high performance, low power, small area and high efficiency. This paper will use the context of a DSP core design to examine a small subset of the full range of design techniques that can be leveraged to directly impact the overall energy efficiency of a design: clock gating and structured clock trees, pulse latches and other multi-bit design structures, 8T vs 6T SRAM arrays, low-voltage retention vs power collapse, aggressive process-variation-aware frequency/voltage scaling with support for both run-fast-and-sleep and just-in-time execution modes, integrated power management solutions.

A Model for Interlevel Coupling Noise in Multilevel Interconnect Structures

This paper discusses the technology limits placed on the clock switching energy in sequential elements. It proposes a novel pulsed latch that uses a single clocked transistor and consumes close to ten times less clock power than a conventional latch using six clocked transistors. It describes how the new circuit enables additional power savings when virtual grounds, instead of a regular clock, are locally distributed to a group of latches. Finally, the paper discusses how to further reduce the dynamic clock power consumption of the new latch without degrading its timing by feeding it a low-swing clock.

Power-aware multi-voltage custom memory models for enhancing RTL and low power verification

We present, for the first time, a holistic data-path driven transistor-interconnect co-optimization method, which systematically isolates the logic-gate and interconnect-wire dominated data-paths in block-level delay-bins (i.e., sub-binning of delay based bins) to significantly improve accuracy of static and dynamic power estimation. It captures the critical interdependence of transistor architecture (FEOL) including local interconnect, and BEOL metal stack optimization to achieve holistic 10nm (N10) technology optimization at target speeds. Using the proposed method, we drive >2.5x Performance/Watt (PpW) improvement for N10 FinFET SOC design over 14nm (N14). Even with ∼3x higher wire resistance of min metal width, the PpW @target-speed for N10 improves >2.5x over N14 with proper design of metal/via stack, transistor Vt and fin-profile as well as standard-cell architecture. Reducing active fin-count and routing distance between standard-cells is a critical design knob for N10 mobile SOC enablement. The proposed methodology enables smartphone-usage (days-of-use) based technology optimization, driving longer battery-life in mobile SOCs, keeping process cost and complexity at minimum.

Clock Gating System and Method

In multilevel interconnect structures, the interconnect layers are practically always perpendicular to each other. Due to the capacitive coupling between adjacent layers, the switching activity in one layer produces noise in the others. Often, this interlevel coupling noise is implicitly neglected: only the parallel neighbors of a victim line are considered noisy while the perpendicular conductors located in the layers above and below the victim are assumed to behave as quiet metal planes. However, the error due to this assumption is unclear. It has never been rigorously analyzed or quantified. This paper examines the interlevel coupling noise present at the far end of a victim when a large number of perpendicular aggressors are randomly switching. Each aggressor is modeled as a Markov chain and the victim is modeled as a resistance-inductance-capacitance transmission line. The result is a novel closed-form expression for the power-spectral density of the random switching noise produced by the perpendicular aggressors. It is used to rigorously show that the quiet metal plane assumption is statistically very good when the number of orthogonal aggressors is large and when they are toggling independently. The validity of the quiet metal plane assumption is also discussed when the orthogonal aggressors form wide buses that can be considered sufficiently correlated to produce deterministic simultaneous switching noise

Logic device and method supporting scan test

We describe a methodology to model the low power and voltage behavior of multi-voltage custom memories in processors. These models facilitate early power-aware verification by abstracting the transistor-level representation of the memory to its power-aware behavioral RTL model. To the best of our knowledge, this is the first attempt at addressing the power-aware RTL model generation problem for custom memories. In our method, we identify voltage crossing points in transistors across channel connected components and use these crossing points to transform the RTL for power-awareness closely matching its circuit implementation. Without the proposed abstraction technique to generate power-aware RTL, low-power verification of such memories will need to be done using transistor-level simulations that are prohibitively time-intensive and hence impractical. We check for correctness of these generated power-aware memory models through formal equivalence, symbolic simulations, assertion and simulation based verification. These models are also validated using static power-domain checks. By applying this methodology in a power-aware design and verification framework on a commercial processor, we identified and corrected low power circuit and RTL bugs prior to tape-out.