Prayag B. Patel

Cost effective 28nm LP SoC technology optimized with circuit/device/process co-design for smart mobile devices

With newer technology nodes, circuit/device/process codesign is essential to realize the advantages of scaling. Leveraging co-design approach based on a well-established manufacturing flow, a cost effective 28 nm 4G SOC technology has been crafted. This 28 nm design strategy uses two sets of design rules and 7 different Vt cells with optimal power gating to achieve a 2.4× increase in gate density, 55% decrease in power and 30% gain in frequency with respect to the 45 nm counterpart. Relevant technical tradeoffs between the design/technology interactions are discussed to illustrate the codesign aspects.

A new statistical setup and hold time definition

Process variability becomes prominent for circuits using nanometer manufacturing technology. With aggressive voltage scaling, unexpected failures occur due to excessive timing variation. Yield, number of components, and process variability are intrinsically linked. In this paper, we study the setup and hold time definition, margin, and characterization methodology. A new statistical margin quantifying methodology, setup and hold time definition and characterization methodology are proposed.

Experiments and analysis to characterize logic state retention limitations in 28nm process node

Mobile devices spend most of the time in standby mode. Supported features and functionalities are increasing in each newer model. With the wide spread adaptation of multitasking in mobile devices, retaining current status and data for all active tasks is critical for user satisfaction. Extending battery life in portable mobile devices necessitates the use of minimum possible energy in standby mode while retaining present states for all active tasks. This paper for the first time, explains the low voltage data-retention failure mechanism in flops. It analyzes the impact of design and process parameters on the data retention failure. Statistical nature of data retention failure is established and validated with extensive Monte-Carlo simulations across various process corners. Finally, silicon measurement from several 28nm industrial mobile chips is presented showing good correlation of retention failure prediction from simulation.

Analysis, modeling and silicon correlation of low-voltage flop data retention in 28nm process technology

Mobile devices spend most of the time in standby mode. Supported features and functionalities are increasing in each newer model. With the wide spread adaptation of multi-tasking in mobile devices, retaining current status and data for all active tasks is critical for user satisfaction. Extending battery life in portable mobile devices necessitates the use of minimum possible energy in standby mode while retaining present states for all active tasks. This paper for the first time, explains the low-voltage data-retention failure mechanism in ops. It analyzes the impact of design and process parameters on the data-retention failure. Statistical nature of data retention failure is established and validated with extensive Monte-Carlo simulations across various process corners. Finally, silicon measurement from several 28nm industrial mobile chips is presented showing good correlation of retention failure prediction from simulation.