Martin Simon

A quad-band low power single chip direct conversion CMOS transceiver with /spl Sigma//spl Delta/-modulation loop for GSM

This paper presents a fully integrated quad band GSM transceiver with a new sigma-delta modulator architecture designed in a standard 120 nm CMOS technology. The fully integrated VCO operates at 4 GHz with a frequency range that can be programmed by 10 bit. The output power of the transmitter is 8 dBm and no TX SAW filter is needed due to the low phase noise of -162 dBc/Hz at 20 MHz offset frequency. The inband phase noise of the synthesizer is only -100 dBc/Hz and an overall phase noise error of 1.6/spl deg/ rms has been measured. The receiver has constant gain of 57 dB and fits to a baseband processor providing a 14 bit ADC. The noise figure in all bands is below 3 dB typically. The chip is housed in a 48 pin VQFN package.

An 802.11a/b/g RF Transceiver in an SoC

The RF transceiver of a 0.13mum CMOS WLAN 802.11 a/b/g SoC for cellular applications comprising MAC, PHY, and analog front-end is presented. The transceiver with direct-conversion architecture and broadband 12GHz VCO draws 87/104mA in TX and 69/80mA in RX mode for the 2.4/5.0GHz band. The TX with control loop achieves -32dB EVM at -2dBm output power with 1.5V supply.

A Multimode Receiver Front-end for Software Defined Radio

A flexible multimode receiver architecture for software defined radio systems with focus on GSM, WCDMA and CDMA systems has been designed in a 120 nm CMOS technology. The receiver consists of a wideband coilless common gate LNA2 with gain switches and a high linearity down-converter with current interface between mixer and baseband-filter. The LO signal of a 8 GHz VCO and divider with ratio 4 respectively 8 covers the whole receiver frequency range. The receiver consumes 32 mA at 1.5 V supply voltage

A CMOS quad-band-/spl Sigma//spl Delta/-transceiver for GSM-EDGE with dual mode transmitter architecture for low noise and high linearity

A 120 nm CMOS quad-band transceiver for GSM EDGE with a dual mode transmitter architecture and a constant gain direct conversion receiver has been developed. In GMSK mode, a direct conversion transmitter with third order /spl Sigma//spl Delta/-modulation loop modulates the phase of the VCO. The output signal is amplified by a low noise power efficient limiting output buffer with 6 dBm output power. A high linearity vector modulator is switched on to process the 8-PSK modulated EDGE signal with additional amplitude modulation. Neither TX-SAW nor third harmonic filter are needed for system integration into a handset to fulfil the GSM-EDGE specification.

An OFDM MIMO Transmitter for Wireless Gigabit with Advanced Multimedia (WIGWAM)

A fully integrated high linearity low power and low cost transmitter in 120 nm CMOS technology with 2 RF-paths and integrated balun for broadband OFDM MIMO application is presented. The transmitter is used for the Wireless Gigabit with Advanced Multimedia (WIGWAM) research project. A maximum datarate of 970 Mbit/s can be achieved by transmitting a 256QAM OFDM MIMO signal with 80 MHz bandwidth and 7/8 code rate. The Error Vector Magnitude is only -28 dB due to low phase noise and high linearity. The RF coupling between the 2 MIMO TX paths is 32 dB. The carrier and sideband of the vector modulator are calibrated with an integrated down-conversion mixer.