Burkhard Neurauter

A CMOS quad-band-/spl Sigma//spl Delta/-transceiver for GSM-EDGE with dual mode transmitter architecture for low noise and high linearity

A 120 nm CMOS quad-band transceiver for GSM EDGE with a dual mode transmitter architecture and a constant gain direct conversion receiver has been developed. In GMSK mode, a direct conversion transmitter with third order /spl Sigma//spl Delta/-modulation loop modulates the phase of the VCO. The output signal is amplified by a low noise power efficient limiting output buffer with 6 dBm output power. A high linearity vector modulator is switched on to process the 8-PSK modulated EDGE signal with additional amplitude modulation. Neither TX-SAW nor third harmonic filter are needed for system integration into a handset to fulfil the GSM-EDGE specification.

Fractional-N Phase Locked Loops and It’s Application in the GSM System

This paper presents an overview of the fractional-N frequency synthesis technique. After a short excursion into the history of δσ modulation, different fractional-N techniques are shown. Following this, the δσ fractional-N PLL is explored in detail, and important results relating to fractional-N PLLs are presented. In the next section the blocks of the analogue part of the PLL are listed, and relevant design criterions are discussed. Finally the specifications imposed by the GSM system are mentioned, and two techniques for using a fractional-N PLL as a GMSK modulator are shown.