Martín Vazquez

FPGA Implementations of BCD Multipliers

This paper presents a number of approaches to implement decimal multiplication algorithms on Xilinx FPGA’s. A variety of algorithms for basic one by one digit multiplication are proposed and FPGA implementations are presented. Later on N by one digit and N by M digit multiplications are studied. Time and area results for sequential and combinational implementations show better figures compared with previous published work. Comparisons against binary fully-optimized multipliers emphasize the interest of the proposed design techniques.

Decimal addition in FPGA

This paper presents a study of the classical BCD adders from which a carry-chain type adder is redesigned to fit within the Xilinx FPGAs. Some new concepts are presented to compute the P and G functions for carry-chain optimization purposes. Several alternative designs are then presented with the corresponding time performances and area consumption figures. In order to compare the results, the straight implementation of a decimal ripple-carry adder and the FPGA optimized base 2 adder for the same range are implemented. Results for big operands show that the decimal adder works faster than an equivalent binary implementation and furthermore the coding / decoding processes are no more needed.

Decimal Adders/Subtractors in FPGA: Efficient 6-input LUT Implementations

This paper presents FPGA implementations of add/subtract algorithms for 10´s complement BCD numbers. Carry-chain type circuits have been designed on 6-input LUT´s Xilinx Virtex-5 FPGA technologies. Some new concepts are reviewed to compute the P and G functions for carry-chain optimization purposes. Designs are presented with the corresponding time performances and area consumption figures. Results have been compared with 2´s complement binary implementations carried out on the same platform. Better time delays have been registered for decimal number within same range of operands.

Experiences applying framework-based functional verification to a design for programmable logic

This paper presents experiences in applying modern functional verification to a configurable decimal floating point Adder / Subtractor core targeted to programmable logic. Despite its huge input space, a number of hard-to-verify corner cases are identified. Two different verification frameworks were applied in order to develop testbenches: OVM and Truss. These tesbenches were built to be independent of the ALU operand representation and IEEE754-2008 specific modules were also implemented. Verification results, the experience itself, and a comparative study of the alternatives was made and summarized for designers and verification engineers.

A FPGA IEEE-754-2008 decimal64 Floating-Point adder/subtractor

This paper describes the FPGA implementation of a Decimal Floating Point (DFP) adder/subtractor. The design performs addition and subtraction on 64-bit operands that use the IEEE 754-2008 decimal encoding of DFP numbers and is based on a fully pipelined circuit. The design presents a novel hardware for pre-signal generation stage and an enhanced version of previously published leading zero stage. The design can operate at a frequency of 200 MHZ on a Virtex-5 with a latency of 8 cycles. The presented DFP adder/subtractor supports operations on the decimal64 format and it is easily extendable for the decimal128 format. To our knowledge, this is the first hardware FPGA design for adding and subtracting IEEE 754-2008 using decimal64 encoding.

High-speed FPGA 10's complement adders-subtractors

This paper first presents a study on the classical BCD adders from which a carry-chain type adder is redesigned to fit within the Xilinx FPGAs platforms. Some new concepts are presented to compute the Pand Gfunctions for carry-chain optimization purposes. Several alternative designs are presented. Then, attention is given to FPGA implementations of add/subtract algorithms for 10s complement BCD numbers. Carry-chain type circuits have been designed on 4-input LUTs (Virtex-4, Spartan-3) and 6-input LUTs (Virtex-5) Xilinx FPGA platforms. All designs are presented with the corresponding time performance and area consumption figures. Results have been compared to straight implementations of a decimal ripple-carry adder and an FPGA 2s complement binary adder-subtractor using the dedicated carry logic, both carried out on the same platform. Better time delays have been registered for decimal numbers within the same range of operands.

FPGA-specific decimal sign-magnitude addition and subtraction

ABSTRACT The interest in sign-magnitude (SM) representation in decimal numbers lies in the IEEE 754-2008 standard, where the significand in floating-point numbers is coded as SM. However, software implementations do not meet performance constraints in some applications and more development is required in programmable logic, a key technology for hardware acceleration. Thus, in this work, two strategies for SM decimal adder/subtractors are studied and six new Field Programmable Gate Array (FPGA)-specific circuits are derived from these strategies. The first strategy is based on ten’s complement (C10) adder/subtractors and the second one is based on parallel computation of an unsigned adder and an unsigned subtractor. Four of these alternative circuits are useful for at least one area-time-trade-off and specific operand size. For example, the fastest SM adder/subtractor for operand sizes of 7 and 16 decimal digits is based on the second proposed strategy with delays of 3.43 and 4.33 ns, respectively, but the fastest circuit for 34-digit operands is one of the three specific implementations based on C10 adder/subtractors with a delay of 4.65 ns.

Design and implementation of decimal fixed-point square root in LUT-6 FPGAs

This paper presents the design and implementation of a digit-recurrence algorithm for determining the decimal square root in a 6-input LUT-based FPGA device. The design is based on the efficient use of resources such as the carry-chain originally devoted to the binary addition. Clock frequencies of 98.5 MHz (71 ns latency), 93.4 Mhz (173 ns latency) and 84.7 MHz (402 ns latency) were obtained for operand widths of 7, 16 and 34 digits, respectively, in a Xilinx Virtex 6 FPGA.