Elías Todorovich

High Resolution FPGA DPWM Based on Variable Clock Phase Shifting

This letter proposes a very high resolution digital pulsewidth modulator (DPWM) architecture that takes advantage of a field-programmable gate array (FPGA) advanced clock management capability - the fine phase shifting of the clock. This feature is available in almost every FPGA nowadays, thus allowing very small and programmable delays between the input and output clocks. An original use of this fine phase shifting pushes the limits of DPWM resolution. The experimental results show a time resolution of 19.5 ps in a Virtex-5 FPGA.

Genetic algorithms and fuzzy control: a practical synergism for industrial applications

A way to automatically generate fuzzy controllers (FCs) that are optimized according to a merit figure is presented in this article. To achieve this task, a procedure based on hierarchical genetic algorithms (HGA) was developed. This procedure and the manner in which fuzzy controllers are codified into chromosomes is described. Resorting to this tool, several fuzzy controllers were constructed. The best three solutions obtained during simulation were selected for testing using an experimental prototype, which consists of an induction motor of variable load. These preliminary results are also included in the report. Based on these results, it is concluded that hierarchical genetic algorithms, though not the only, is a suitable artificial intelligence technique to face the problem of setting a fuzzy controller in a control loop without previous experience in controlling the plant. This is of help in many situations at industrial environments.

FPGA Implementations of BCD Multipliers

This paper presents a number of approaches to implement decimal multiplication algorithms on Xilinx FPGA’s. A variety of algorithms for basic one by one digit multiplication are proposed and FPGA implementations are presented. Later on N by one digit and N by M digit multiplications are studied. Time and area results for sequential and combinational implementations show better figures compared with previous published work. Comparisons against binary fully-optimized multipliers emphasize the interest of the proposed design techniques.

Low-Power FSMs in FPGA: Encoding Alternatives

In this paper, the problem of state encoding of FPGA-based synchronous finite state machines (FSMs) for low-power is addressed. Four codification schemes have been studied: First, the usual binary encoding and the One-Hot approach suggested by the FPGA vendor; then, a code that minimizes the output logic; finally, the so-called Two-Hot code strategy. FSMs of the MCNC and PREP benchmark suites have been analyzed. Main results show that binary state encoding fit well with small machines (up to 8 states), meanwhile One-Hot is better for large FSMs (over 16 states). A power saving of up to the 57 % can be achieved selecting the appropriate encoding. An area-power correlation has been observed in spite of the circuit or encoding scheme. Thus, FSMs that make use of fewer resources are good candidates to consume less power.

DPWM based on FPGA clock phase shifting with time resolution under 100 ps

This paper proposes a new DPWM architecture that takes advantage of FPGApsilas advanced clock management capabilities. The feature used in this investigation is that the clock management system nowadays present in almost every FPGA allows fine phase shifting of the clock. This is not only true for high-end and expensive FPGAs. Using a low cost FPGA, like Xilinx Spartan-3, the clock can be phase shifted in steps that range from 30 to 60 ps. This opens new possibilities for pushing the limits of DPWM resolution. The experimental results show two alternative DPWMs that obtain a time resolution under 100 ps while maintaining high linearity and monotonic behavior.

FSM Decomposition for Low Power in FPGA

In this paper, the realization of low power finite state machines (FSMs) on FPGAs using decomposition techniques is addressed. The original FSM is divided into two submachines using a probabilistic criterion. Only one submachine is active at a time, meanwhile the other is disabled to save power. Different deactivation alternatives and state encoding have been studied. For each option, actual measurements of power consumption have been done using the MCNC and the PREP benchmark circuits. A Xilinx XC4K device has been utilized as technological framework. The proposed technique fits well with big FSM, where power reductions up to 46% are obtained.

Statistical power estimation for FPGAs

This article presents a power estimation tool integrated with an FPGA design flow. It is able to estimate total and individual-node average power consumption for combinational blocks. The tool is based on the statistical approach, allowing the user to specify the tolerated error and confidence level of the power estimation. An important feature of this software is the short pulse filtration that leads, in other case, to overestimation. Power maps generation is implemented to help both to detect hot-spots, and perform a power optimization. These maps show the power at every physical position in the die. Several circuits have been tested in order to demonstrate the tool features and usability. The estimated values of dynamic power have been compared with physical measurements for Virtex and Virtex-E devices.

Resolution Analysis of Switching Converter Models for Hardware-in-the-Loop

This work proposes two methods to determine the resolution of state variables in models of switching-mode power converters. The target models are intended for hardware-in-the-loop, i.e., closed-loop emulation using a model of the power converter implemented in digital hardware with the controller in its final implementation. The focus here is on the resolution of fixed-point models, although the results can also be applied to the significand resolution in floating-point representation. The first method is based on the simulation, provides the designer with the optimum resolution values, and guarantees that using the resolution, the converter will behave as it was specified. The second method is fast but conservative, intended for applications without hard constraints of area and speed. Despite the simplicity of the second method, its results, although slightly overestimated, have been demonstrated to be correct by the results of the first method. A boost converter for the power factor correction is used as an application example. As the converter model is intended for field-programmable gate array implementation, its area and maximum clock frequency are also analyzed. In this application example, the results show that the area grows linearly with the number of bits of each state variable, and the clock frequency is dominated by the width of one of the variables.

A co-design methodology for processor-centric embedded systems with hardware acceleration using FPGA

In this work a co-design flow for processor centric embedded systems with hardware acceleration using FPGAs is proposed. This flow helps to reduce design effort by raising abstraction level while not imposing the need for engineers to learn new languages and tools. The whole system is designed using well established high level modeling techniques, languages and tools from the software domain. That is, an OOP design approach expressed in UML and implemented in C++. Software coding effort is reduced since the C++ implementation not only provides a golden reference model, but may also be used as part of the final embedded software. Hardware coding effort is also reduced. The modular OOP design facilitates the engineer to find the exact methods that need to be accelerated by hardware using profiling tools, preventing useless translations to hardware. Moreover, the two-process structured VHDL design method used for hardware implementation has proven to reduce man-years, code lines and bugs in many major developments. A real-time image processing application for multiple robot localization is presented as a case study. The overall time improvement from the original software solution to the final hardware accelerated solution is 9.7×, with only 4% increase in area (143 extra slices). The embedded solution achieved following the proposed methodology runs 17% faster than in a standard PC, and it is a much smaller, cheaper and less power-consuming solution.

Experiences applying OVM 2.0 to an 8B/10B RTL design

The SystemVerilog implementation of the Open Verification Methodology (OVM) is exercised on an 8b/10b RTL open core design in the hope of being a simple yet complete exercise to expose the key features of OVM. Emphasis is put onto the actual usage of the verification components rather than a complete verification flow aiming at being of help to readers unfamiliar with OVM seeking to apply the methodology to their own designs. A link that takes you to the complete code is given to reinforce this aim. We found the methodology easy to use but intimidating at first glance specially for someone with little experience in object oriented programming. However it is clear to see the flexibility, portability and reusability of verification code once you manage to give some first steps.