Mary L. Bailey

Parallel logic simulation of VLSI systems

Fast, efficient logic simulators are an essential tool in modern VLSI system design. Logic simulation is used extensively for design verification prior to fabrication, and as VLSI systems grow in size, the execution time required by simulation is becoming more and more significant. Faster logic simulators will have an appreciable economic impact, speeding time to market while ensuring more thorough system design testing. One approach to this problem is to utilize parallel processing, taking advantage of the concurrency available in the VLSI system to accelerate the logic simulation task. Parallel logic simulation has received a great deal of attention over the past several years, but this work has not yet resulted in effective, high-performance simulators being available to VLSI designers. A number of techniques have been developed to investigate performance issues: formal models, performance modeling, empirical studies, and prototype implementations. Analyzing reported results of these techniques, we conclude that five major factors affect performance: synchronization algorithm, circuit structure, timing granularity, target architecture, and partitioning. After reviewing techniques for parallel simulation, we consider each of these factors using results reported in the literature. Finally we synthesize the results and present directions for future research in the field.

How circuit size affects parallelism

The author addresses the issue of how well circuit parallelism scales with circuit size. Empirical studies using a single representation, switch-level, and two different timing models are presented. The results show that, in general, parallelism does not scale linearly with circuit size, and that the relationship between parallelism and circuit size is much more complex. The author first describes the simulators and methodology used to measure circuit parallelism. The circuit parallelism and percentage of parallelism of nine circuits, ranging in size from 200 to 61600 transistors, are described. Parallelism measurements from different instances of three circuit families are presented to show that, even within circuit families, relative parallelism is not constant for different instances. >

A time-based model for investigating parallel logic-level simulation

A model for studying the effects of timing models and synchronization strategies for event-driven parallel logic-level simulation is presented. Two timing models, variable-delay and unit-delay, and two synchronization strategies, synchronous and conservative asynchronous, are discussed. The average parallelism of circuits using the two timing models are compared, and the execution times of circuits using various timing models and synchronization strategies are considered. It is shown that the circuit parallelism using unit-delay timing provides an upper bound on that of any timebase used in variable-delay timing and that with either timing model, the execution time of the conservative asynchronous strategy is a lower bound over the synchronous strategy, assuming an unlimited number of processors. However, assuming that all events take the same amount of time, it is shown that with unit-delay timing, the execution time of the synchronous strategy equals that of the asynchronous strategy. >

Using ZPL to develop a parallel chaos router simulator

This paper reports on our experience in writing a parallel version of a chaos router simulator using the new data driven parallel language ZPL. The simulator is a large program that tests the capabilities of ZPL. The (parallel) ZPL program is compared with the existing serial implementation on two very different architectures: a 16-processor Intel Paragon and a cluster of eight Alpha work stations. On the Paragon, the simulator performs best when simulating medium- to large-sized routers, and on the Alpha cluster, it performs best when simulating large routers. Thus a user can choose the parallel platform best suited to the router size.

Measuring the overhead in conservative parallel simulations of multicomputer programs

It is shown that it is feasible to characterize the overheads present in conservative parallel simulations of multicomputer programs. The authors use a modified version of the parallel simulator from the Poker programming environment to empirically measure the overhead in two parallel algorithms which use three different interconnection structures. They discuss the sources of overhead and qualitatively discuss their relative importance.<<ETX>>

Empirical measurements of overheads in conservative asynchronous simulations

In order to make formal and analytic models more realistic, overheads which were previously ignored or vastly simplified must be included. We consider the feasibility of characterizing the overheads in conservative asynchronous simulations for such models, and we focus on a single communication structure (i.e., meshes) and use both multicomputer programs and a queueing network as example applications. We find that the two most important issues for modeling are to understand how to estimate the time spent in sending null messages and how to account for the resulting overhead due to the input waiting rule. For null messages, we estimate both the number of messages sent as well as the cost per null message. The number of messages sent can often be estimated by the application, although irregularities in communication structure and edge effects in communication can affect these estimates. A constant is valid as a first-order approximation for the time per null message, but there are secondary factors that one may wish to model, such as load balancing and communication irregularities. The overhead attributable to the input waiting rule depends on several factors: communication structure, communication frequency, and processor load balancing. Irregularity in any of these dimensions can adversely affect the performance of the conservative strategy. It appears feasible to use the factors contributing to the overheads (i.e. context switch costs; null-message costs; percentage of looping due to the conservative synchronization) in a formal model to estimate the cost of the conservative overheads.

A model for comparing synchronization strategies for parallel logic-level simulation

The authors apply a formal model described by M.L. Bailey and L. Snyder (Distributed Simulation, SCS, 1989, p.157-63) to the more difficult problem of comparing three different synchronization strategies: synchronous, conservative asynchronous, and optimistic asynchronous. They show that with unlimited processors, for variable-delay and unit-delay timing, conservative<or=syncrhonous, and that optimistic may be the best. They also show that if the event evaluation times are equal, the execution times for conservative asynchronous and synchronous strategies are equal for unit-delay timing. The restriction of requiring unlimited processors for these results is addressed.<<ETX>>

CNI: a high-performance network interface for workstation clusters

Networks of workstations provide an economic solution for scalable computing because they do not require specialized components. Even though recent advances have shown that it is possible to obtain high bandwidth between applications, interconnect latency remains a serious concern. We present CNI, a cluster network interface that not only provides both low latency and high bandwidth but also efficiently supports multiple programming paradigms. This is done by functionally coupling the network adaptor board more closely to the CPU without changing the standard workstation architecture. CNI results in performance gains for applications, substantially reducing communication overhead and delay.

How using busses in multicomputer programs affects conservative parallel simulation

In this paper we consider the effect of using bus interconnection structures on the overheads present in conservative parallel simulations of multicomputer programs. We use a modified version of the Poker Programming Environment to empirically measure the overhead in three parallel algorithms using buses. We discuss the sources of overhead and compare them with those found using point-to-point communication. Preliminary results indicate that the overheads encountered using a bus interconnection structure were not predicted by our previous results using point-to-point communications.

A delay-based model for circuit parallelism

A new formal model for variable-delay simulators is presented for comparing the effects of time base on circuit parallelism. This model more accurately reflects current simulation strategies than previous models. Using this new model the author shows that parallelism is not a nondecreasing function of time base. She bounds parallelism, however, by two functions that converge to the unit-delay parallelism as the time base increases, preserving the intuition that coarser timing models result in greater parallelism. In addition, the author corroborates the model predictions via an empirical study and discusses the impact of the results on synchronous and conservative asynchronous parallel simulations. >