Marylyn Hoy Bennett

Automatic defect classification: status and industry trends

As device geometries shrink to 0.25 micron and smaller, all facets of integrated circuit (IC) processing are being challenged. With device sizes shrinking, so too shrinks the size of a defect that can cause chip failure, and hence yield loss. Contamination free manufacturing practices are becoming critical for successful device fabrication. To accomplish this, elimination of defect sources has a high priority. A defect can be a particle, microcontamination, pattern anomaly, crystalline defect such as a stacking fault, and so on. Defects have become a main source of yield loss to the semiconductor industry. This comes at a time when 90% yield values on mature product cannot increase at the rate that has occurred in the past. The industry is now faced with finding methods of incremental yield increase, in-line, on production wafers. Automatic Defect Classification (ADC) is an important part of SEMATECHs strategy to meet these industry needs.

Experimental measurements of diffraction for periodic patterns by 193-nm polarized radiation compared to rigorous EMF simulations

Polarization dependent diffraction efficiencies in transmission through gratings on specially designed masks with pitch comparable to the wavelength were measured using an angle-resolved scatterometry apparatus with a 193 nm excimer source. Four masks - two binary, one alternating and one attenuated phase shift mask - were included in the experimental measurements. The validity of models used in present commercially available simulation packages and additional polarization effects were evaluated against the experimental scattering efficiencies.

Photomask dimensional metrology in the scanning electron microscope, part II: High-pressure/environmental scanning electron microscope

Binary and phase-shifting chromium on quartz optical photomasks have been successfully investigated with high-pressure/environmental scanning electron microscopy (SEM). The successful application of this methodology to semiconductor photomask metrology is new because of the recent availability of high-pressure SEM instrumentation equipped with high-resolution, high-signal, field emission technology in conjunction with large chamber and sample transfer capabilities. The high-pressure SEM methodology employs a gaseous environment to help diminish the charge buildup that occurs under irradiation with the electron beam. Although very desirable for charge reduction, this methodology has not been employed in production photomask or wafer metrology until now. This is a new application of this technology to this area, and it shows great promise in the inspection, imaging and metrology of photomasks in a charge-free operational mode. This methodology also holds the potential of similar implications for wafer metrology. For accurate metrology, high-pressure SEM methodology also affords a path that minimizes, if not eliminates, the need for charge modeling. This paper presents some new results in high-pressure SEM metrology of photomasks.

Meeting advanced pattern inspection system requirements for 0.25-μm technology and beyond

An advanced in-line patterned wafer defect detection system has been developed in a Joint Development Project (JDP) with Tencor Instruments and SEMATECH. The JDP, known as J101, was initiated due to critical needs identified in a SEMATECH Phase 4/5 (0.25 micrometers ) Workshop. The goal of the workshop was to identify the most suitable and cost-effective technology to meet the in-line monitoring needs specified in the National Technology Roadmap for Semiconductors (NTRS), also known as the SIA technology roadmap. This paper will review the inspection requirements identified in the SEMATECH Phase 4/5 (0.25 micrometers ) Workshop, specify the objectives and milestones of the JDP, provide a technology overview of the system, and show results obtained by using the system during alpha and prototype characterization.

Photomask dimensional metrology in the scanning electron microscope, part I: Has anything really changed?

Photomask dimensional metrology in the scanning electron microscope has not evolved as rapidly as the metrology of resists and integrated circuit features on wafers. This has been due partly to the 43 (or 53) reduction in optical steppers and scanners used in the lithog- raphy process, and partly for the lesser need to account for the real three dimensionality of the mask structures. So, where photomasks are con- cerned, many of the issues challenging wafer dimensional metrology at 13 are reduced by a factor of 4 or 5 and thus could be temporarily swept aside. This is rapidly changing with the introduction of advanced masks with optical proximity correction and phase shifting features used in 100 nm and smaller circuit generations. Fortunately, photomask metrology generally benefits from the advances made for wafer metrology, but there are still unique issues to be solved in this form of dimensional metrology. It is likely that no single metrology method or tool will ever provide all necessary answers. As with other types of metrology, resolu- tion, sensitivity and linearity in three-dimensional measurements of the shape of the lines and phase shifting features in general (width, height and wall angles) and departure from the desired shape (surface and edge roughness, etc.) are the key parameters. Different methods and tools differ in their capability to collect average and localized signals at acceptable speed, but in any case, application of thorough knowledge of the physics of the given metrology is essential to extract the information needed. This paper will discuss the precision, accuracy and traceability in SEM metrology of photomasks. Current and possible new techniques utilized in the measurements of photomasks including suppression of charge and highly accurate modeling for electron beam metrology will also be explored to answer the question, Has anything really

Particle generation mechanisms in vacuum processing tools

It is estimated that by the year 1995, as much as ninety percent of the contamination in IC manufacturing will be caused by equipment and processes. Contamination can be in the form of particles, defects, scratches, stains, and so on. All are major concerns for yielding ULSI devices. In order to eliminate process/equipment-induced particles, particle formation/generation must be understood before appropriate action can be taken to meet the contamination-free requirements of the future. A variety of vacuum processing tools were studied, including CVD, PECVD, and plasma etch systems with heat lamps, RF, and remote microwave energy sources. A particle collection and characterization methodology was adopted to analyze the particles generated from the vacuum processing tools. By using SEM and EDS to analyze particles collected from equipment chamber walls, both the particle morphology and composition were discerned. The elemental analyses indicate that the composition of particles varied a great deal depending on the chemical nature of the process, chamber material/process compatibility, and energy source.

Photomask dimensional metrology in the SEM: Has anything really changed?

Photomask dimensional metrology in the scanning electron microscope (SEM) has not evolved as rapidly as the metrology of resists and integrated circuit features on wafers. This has been due partly to the 4x (or 5x) reduction in the optical steppers and scanners used in the lithography process, and partly for the lesser need to account for the real three-dimensionality of the mask structures. So, where photomasks are concerned, many of the issues challenging wafer dimensional metrology at 1x are reduced by a factor of 4 or 5 and thus could be temporarily swept aside. This is rapidly changing with the introduction of advanced masks with optical proximity correction and phase shifting features used in 100 nm and smaller circuit generations. Fortunately, photomask metrology generally benefits from the advances made for wafer metrology, but there are still unique issues to be solved in this form of dimensional metrology. It is likely that no single metrology method or tool will ever provide all necessary answers. As with other types of metrology, resolution, sensitivity and linearity in the three-dimensional measurements of the shape of the lines and phase shifting features in general (width, height and wall angles) and the departures from the desired shape (surface and edge roughness, etc.) are the key parameters. Different methods and tools differ in their ability to collect averaged and localized signals with an acceptable speed, but in any case, application of this thorough knowledge of the physics of the given metrology is essential to extract the needed information. This paper will discuss the topics of precision, accuracy and traceability in the SEM metrology of photomasks. Current and possible new techniques utilized in the measurements of photomasks including charge suppression and highly accurate modeling for electron beam metrology will also be explored to answer the question “Has anything really changed?”

Semiconductor Factory Control and Optimization

The sections in this article are 1 Control in Breadth 2 Generic Model of the Elements of a Controller 3 Control in Depth 4 Change Management 5 Statistical Process Control 6 Run-to-Run Model-Based Process Control 7 Equipment Signal Monitoring, Real-Time Fault Detection and Classification 8 Sensors 9 In Situ Particle Monitors 10 In-Line Defect Monitoring and Contamination Control 11 Wafer Position Tracking 12 Data Mining and Data Warehousing 13 Parametric and Yield Outlier Control 14 Wafer Level Reliability Control 15 Multivariate SPC, Especially for Equipment Signal Monitoring 16 Acknowledgments

Particle metrology for microelectronics

Particles, defects, and microcontaminaton: the bane of the IC process engineer! Controlling defects during every processing step of semiconductor devices is vital to successful manufacturing of modem chips. The requirements for tight defect control become increasingly severe with each new generation of semiconductors. For a typical 16 MB DRAM process, the total number of defects must be less than one for each 4 cm2 Gf Wafer surface area in order to achieve 70% yield on the wafer.1 Not only must the total number of defects on wafers decrease with each generation, the defect concentration per mask level must be reduced at an ever faster rate due to higher circuit complexity and increased number of mask levels. These defect reduction requirements are noted here for DRAMs, used as the technology driver, but must also be achieved in other device families such as ASICs and microprocessors.Particles, defects, and microcontaminaton: the bane of the IC process engineer! Controlling defects during every processing step of semiconductor devices is vital to successful manufacturing of modern chips. The requirements for tight defect control become increasingly severe with each new generation of semiconductors. For a typical 16 MB DRAM process, the total number of defects must be less than one for each 4 cm2 of wafer surface area in order to achieve 70% yield on the wafer.l Not only must the total number of defects on wafers decrease with each generation, the defect concentration per mask level must be reduced at an ever faster rate due to higher circuit complexity and increased number of mask levels. These defect reduction requirements are noted here for DRAMs, used as the technology driver, but must also be achieved in other device families such as ASICs and microprocessors. 2. INTRODUCTION The trend for device manufacturing over the years involves shrinking design rules smaller and smaller, while at the same time putting more and more features onto a single chip. The chip size often remains the same, but in the case of DRAMs is projected to approximately double with each new generation. The number of lithography, film, and metal levels are also increasing which further complicates processing.2 Semiconductor houses are further pushing to decrease the design -toproduction time to get the most market share possible. All the while, the size of the killing defects becomes smaller and smaller. Table 1 shows the killing defect size versus minimum feature size. The device currently under development by the leading edge companies is the 256 MB DRAM. As can be seen in the table, the minimum feature size is 0.25 micron, squeezing four times the memory onto only twice the chip area of the previous generation, with the killing defect size at 0.05 micron. The hidden problem with this generation is that no defect detection tool exists today to detect lower than 0.1 micron!

Stepper Lens Characterization Using A Field Emission SEM

A method of stepper lens evaluation has been developed which utilizes a simple resolution test pattern of the type usually supplied with the stepper. Measurements are made using an automated field emission SEM equipped to perform whole wafer non-destructive critical dimension analysis. Measurement data on focus and sizing is then analyzed by a computer program easily run on a small personal computer. Information on reticle sizing errors and wafer flatness may also be included in the analysis to minimize errors.