Maryse Wouters

MULTICUBE: Multi-objective Design Space Exploration of Multi-core Architectures

Technology trends enable the integration of many processor cores in a System-on-Chip (SoC). In these complex architectures, several architectural parameters can be tuned to find the best trade-off in terms of multiple metrics such as energy and delay. The main goal of the MULTICUBE project consists of the definition of an automatic Design Space Exploration framework to support the design of next generation many-core architectures.

PICARD: Platform Concepts for Prototyping and Demonstration of High Speed Communication Systems

Nowadays, new and powerful algorithms are developed by telecom engineers to enhance the communication link capacity and robustness. However, the step to build a demonstrator in order to validate the performance of the algorithm is huge. Therefore, we conceived a generic platform that closes this know-how gap by defining reusable modular hardware concepts and Linux driver development software. The hardware concepts feature dedicated high-speeddata links, flexible configurable hardware, integration of Intellectual Property (IP) cores and built-in debug facilities. The boards are Compact PCI compliant and can be plugged in a standard shelf to build a system. These platform concepts will find a first application in the demonstration of a Wireless Local Area Network (WLAN) system.

Real time prototyping of broadband wireless LAN systems

Prototyping of wireless systems gives key insight of the system operation and its performance in a real wireless end-to-end link. The platform provides access to real propagation channels and gives better understanding of the impact of front-end impairments such as phase noise and amplifier non-linearity. In this way it can help the designers to ensure that their system design meets the performance requirements of the wireless LAN standardization committees. We have conceived a generic platform for real time prototyping of broadband WLAN systems. The platform is based on modular multi-FPGA and multi-board concepts with support for high-speed serial connection links between the boards. The hardware and software flexibility of the platform facilitates the extensions towards next generation WLAN standards. This paper describes the implementation of a 54 Mbps single antenna Hiperlan2 wireless LAN user terminal and the implementation of a 2-antenna base station with a downlink capacity of 2 times 54 Mbps. Two realizations of the front-end and their digital compensation techniques are characterized on the platform: a 5 GHz super-heterodyne transceiver and a 5 GHz direct conversion receiver. Finally, a real time WLAN system with medium access control (MAC) is demonstrated on the platform.

The MULTICUBE Design Flow

This chapter introduces the design-flow of the MULTICUBE project whose main goal is the definition of an automatic multi-objective Design Space Exploration (DSE) framework to be used to tune the parameters of System-on-Chip architectures by taking into account the target set of metrics (e.g. energy, latency, throughput, etc.). One of the important goals of the automatic multi-objective DSE framework is to find design trade-offs that best meet system constraints and cost criteria which are indeed strongly dependent on the target application.A set of heuristic optimisation algorithms have been defined to reduce the overall optimization time by identifying an approximated Pareto set of parameter configurations with respect to a set of selected figures of merit. Once the approximated Pareto set is built, the designer can quickly apply decision criteria to select the best configuration satisfying the constraints. The DSE flow is based on the interaction of two frameworks to be used at design time: the Design Space Exploration Framework, a set of opensource and proprietary architectural exploration tools, and the Power/Performance Estimation Framework, a set of modeling and simulation tools (open-source and proprietary) operating at several levels of abstraction. The DSE flow also includes the specification of an XML integration interface to connect the exploration and estimation frameworks and a Run-time Resource Manager exploiting, at run-time, the best software configuration alternatives derived at design-time to optimize the usage of system resources.

Design of a wideband CTDMA modem for broadband satellite communications

Code division multiple access (CDMA) promises to become the enabling technology for the future generation of satellite communications. For instance, CDMA is being used in Globalstar, Skybridge and is also proposed for the satellite component of UMTS. The evolution of satellite systems towards multimedia communications, necessitates not only wideband CDMA but also requires a hybrid code and time division multiple access (CTDMA) technique because of the packet nature of the data. In this paper, we give an overview of the challenges in designing a wideband CTDMA modem. As a first challenge, the wideband nature of the CDMA modem dictates that the tracking loops of the modem can no longer be executed in software but must be fully integrated in VLSI. Second, the packet based nature of the communication in a CTDMA modem requires ultra fast acquisition for each packet. The extremely low signal-to-noise ratio in satellite communications largely complicates this fast acquisition task.

Wideband TDMA/CDMA terminal modem for broadband satellite multimedia

The time division multiplex/multiple access (TDM/TDMA) scheme has been until now the dominant multiplex/multiple access scheme in satellite communications while code division multiple access (CDMA) is still viewed as too complex and not sufficiently mature by many system designers, specially for high data rate systems. Nevertheless, the high flexibility of CDMA makes it attractive for future broadband satellite multimedia (BSM) systems. Realistic satellite communication systems require a careful system analysis to exploit the potential of CDMA at its best. In this paper, we describe a system concept for BSM relying on a hybrid code and time division multiple access technique and show that the fundamental argument against CDMA, namely receiver complexity, can be overcome. We describe how this system concept can be translated into an efficient modem architecture. We focus on the most critical part-the digital demodulator-that must be capable to sustain a user bit rate in excess of 20 Mbit/s. The main challenges of such demodulator design lie in fast synchronisation, operation at low E/sub b//N/sub 0/, low implementation loss and the complex rate conversion and buffering requirements.