Masa-aki Fukase

Scaling up of wave pipelines

Wave pipelining is a technique of arranging synchronous logic circuits in a pipeline fashion based on delay balancing that allows clocking rate higher than that of well-known regular pipelining. In order to scale up wave-pipelined circuits in the trend of VLSI development toward tighter integration, firstly we investigate scale-dependent characteristics of those circuits with simple structure. It is shown that larger scale is more favorable in view of pipeline degree and vector-execution time. Secondly we explore multifunctional wave pipelines with considerable scales and complicated structures. A fully wave-pipelined structure is recommended to multifunctional circuits regarding software overheads and areas. Thirdly, we show the standard cell synthesis of a fully wave-pipelined scalar processing unit to demonstrate the practicality of wave pipelining multifunctional random logic circuits. By using 0.5-/spl mu/m CMOS technology, a scalar processing unit is implemented in a 2.3-mm/spl times/2.3-mm chip whose clock speed is estimated to be 1 GHz from circuit level simulation.

A Stream Cipher Engine for Ad-Hoc Security

Overall demands of ever growing ubiquitous environment are security, speed, and power consciousness in processing huge amount of multimedia data. Especially, the critical issue is the security threat due to the spread of mobile platforms. Then, ad-hoc security is very important to keep the temporary security of ubiquitous devices without permanent network infrastructure. A practical solution to meet these demands is a safety aware, high- performed single chip processor. According to this scheme, we have exploited hardware cryptography- embedded processors named RAP (random addressing-accelerated processor) and HCgorilla. We have conceived from RAP and HCgorilla a cryptography called RAC (random addressing cryptography). RAC is a practical cipher promising for multimedia streaming that has ability to keep the temporary security of ubiquitous devices without usual network infrastructure. Abstracting the potential feature of RAC from RAP and HCgorilla, we have developed a multimedia stream cipher engine that has a compact multicore processor structure. In this article, we describe the overall architecture and cryptographic structure of the stream cipher engine, RAC run on the stream cipher engine and its ad-hoc aspects compared with usual cipher techniques.A novel license plate locating approach based on the color and texture features is presented. Firstly, the input image is converted to the hue-saturation-intensity (HSI) color space. Then a target image is obtained by applying a sequence of image processing techniques to the hue and saturation component images. After that, the space-pixel histogram of the target image is analyzed and mathematically modeled, so that the horizontal candidate is extracted. Finally, discrete wavelet transform is performed on the candidate, and the sum of the first order difference of the DWT subimages highlights the texture information of the LP area, telling the precise position of the license plate. The proposed algorithm focuses on combining the color features with the texture features, improving the locating reliability. Experiment was conducted on a database of 332 images taken from various illumination situations. The license plate detecting rate of success is as high as 96.4%.

Design of a hardware security-embedded multimedia mobile processor

With respect to privacy on the Internet, it is a matter of keen interest to provision security for multimedia mobile communication. This is characterized by the power conscious high speed cryptography of large quantities of image data. Such demand should be covered by a single VLSI processor system. We describe in this article a hardware security-embedded multimedia mobile processor named HSgorilla by sophisticatedly unifying five up-to-date processor techniques. They are single processor SMT (simultaneous multithreading), VLIW (very long instruction word), wave-pipeline, Java, and random addressing. RAC (random addressing cryptography) achieved by HSgorilla is very promising compared with regular cryptographic operations in view of running time and security strength. Carefully considering the features of image cryptography by RAC, it is a very promising technique in the era of ubiquitous computing.

Hardware/Software Co-design of a Secure Ubiquitous System

Ever growing ubiquitous environment demands security, speed, and power consciousness in processing huge amount of multimedia information. A practical solution to meet these demands is a safety aware, high-performed, and sophisticated architecture. According to this scheme, we have exploited a secure ubiquitous system composed of a hardware cryptography-embedded multimedia mobile architecture and its software support. The architecture is a dedicated single chip processor called HCgorilla. Since one-sided hardware design approach does not always achieve the overall demands for the secure ubiquitous system, we have followed H/S co-design. The software support includes a Java interface and parallelizing compilers run on servers to reduce the load and increase the performance of HCgorilla-embedded clients

Hardware cryptography for ubiquitous computing

Progressive ubiquitous networks have impressed us with alternative features, diversity or security. When the diversity from small devices to large machines is in normal states, ubiquitous networks are functional and useful. But, it is hard to control if abnormal states once happen. Since the diversity brings about open-access to ubiquitous networks anytime anywhere, this really threatens user security. The key to protect huge amount of multimedia data in ubiquitous networks is to introduce safety aware high-performed single VLSI processor systems embedded with cipher process. TPM (trusted platform module) is a cutting-edge technique developed for the front-end security of a ubiquitous device. Since this works for a short, password-size text data, it does not always promise the complete safety of multimedia data stored in the ubiquitous device. In order to solve this fatal issue, we have developed a mobile processor dedicated to multimedia cryptography. This paper focuses on the multimedia cryptography by the dedicated processor.

Development of a multimedia mobile processor

Handheld devices, like cellular phones and PDA (personal digital assistants), have succeeded mainly through the power conscious design of mobile processors. This has resulted in a lack of performable features compared with PCs. Yet, the trend of handheld devices in recent years has been to add sophisticated functions for multimedia processing. Since such a scheme has relied on a software approach, it is hard to achieve high speed with low power. Setting up the drastic throughput of 1 GIPS (10/sup 9/ instructions/sec) and 1 W power dissipation to meet the demand for power, speed, and usability, we have developed a Java-embedded mobile processor core named gorilla. This paper focuses on the design approach to one of gorillas derivatives using 0.35 /spl mu/m CMOS standard cell technology.

Development of a Multimedia Stream Cipher Engine

Ever growing ubiquitous environment makes overall demands for security, speed, and power consciousness in processing huge amount of multimedia data. A practical solution to meet these demands is a safety aware, high-performed, and sophisticated single chip processor. According to this scheme, we have exploited a hardware cryptography-embedded multimedia mobile system composed of a dedicated processor called HCgorilla. A promising cipher technique conceived from this system is RAC (random addressing cryptography). Abstracting the potential feature of RAC from HCgorilla, we focus in this article the development of a multimedia stream cipher engine. This is really suited to the high speed safety communication of large quantity of multimedia data.

Innovative Ubiquitous Cryptography and Sophisticated Implementation

Contemporary ubiquitous network has a double-edged sword or alternative aspects, diversity and threat. While worldwide diversity of ubiquitous platforms has really contributed to enhancing the amenity of our daily life, it is also the cause of illegal attack, intrusion, pretension, etc. Current provisions for information security do not always fulfill overall demands required to ever-growing ubiquitous community. In order to keep usability and achieve safety, we have exploited ubiquitous cryptography named RAC (random number-addressing cryptography). This is an innovative common key technique and has more promising performance than block cipher like DES and AES. Although RAC can be run on any platform, a dedicated processor is more preferable in order to achieve sufficient speed, performance, and strength in the cryptographic streaming of large quantity of ubiquitous information. In order to distinguish these features without deteriorating media processing, we have developed a ubiquitous processor named HCgorilla and its software support. It is a single chip multimedia mobile processor unified sophisticated features of RAC and processor techniques useful for low power, high throughput, and Java. The system combined HCgorilla and the software support works well for media processing as well as ubiquitous cryptography

Chip Design of a Wave-Pipelined PRNG

Wave-pipelining technique has been one of most effective solutions for achieving speed and power conscious logic circuits. This attractive technique has been so far used in developing combinational circuits like adder, multiplier. In order to totally enhance the design activity of logic circuits, we have exploited the wave-pipelining of sequential circuits. Firstly we describe in this paper the wave-pipelining of LFSR (linear feedback shift register). Then, this has been evaluated by using CPLD (complex programmable logic device). From practical viewpoint, LFSR has played important roles as PRNG (pseudo-random number generator) within processors. Thus, we have finally designed the wave-pipelined PRNG by using 1.2-mum CMOS technology. The chip implementation of the waved-PRNG is very promising for highly performable and low-power processor chips

Impact of on-chip interconnects on vertical signal propagation in 3D ICs

Three-dimensional integrated circuits (3D ICs) provide a promising solution for overcoming delay/power problems of 2D ICs by stacking chips vertically. Signal propagation speed among the stacked chips is very important for 3D IC systems. We propose a simple model for analyzing the vertical signal propagation in through-silicon-via-based 3D ICs and discuss the impact of physical parameter variations on propagation delay. Experimental results show that on-chip interconnects greatly affect vertical signal propagation when there are dense general interconnects near the vertical signal interconnect, large amount of fanout, and interconnect length of a driver and receivers is long.