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Featured researches published by Masaaki Harazono.


electronic components and technology conference | 2013

Development of a Low CTE chip scale package

Tomoyuki Yamada; Masahiro Fukui; Kenji Terada; Masaaki Harazono; Charles L. Reynolds; Jean Audet; Sushumna Iruvanti; Hsichang Liu; Scott Preston Moore; Yi Pan; Hongqing Zhang

This paper describes the development of a low CTE organic Chip Scale Package (CSP) jointly by KST and IBM. Tests carried out on the low CTE laminate material and subsequently on the related CSP are described. The new material set, identified as Advanced SLC Package, combines low CTE core and build-up dielectric materials to achieve a composite laminate CTE of 9-12 ppm/°C, which is intermediate between the CTEs of silicon device and conventional board. The lower composite CTE reduces the dimensional mismatch between chip and laminate during Bond and Assembly (BA) to mitigate Chip-Package Interactions (CPI) and white bumps. The low CTE significantly reduces the strain in the solder joints during the reflow process and ensures the solder joint reliability. Global and chip-site warp data from thermo-mechanical modeling are compared to the measured warp data. In addition, other mechanical risk factors for a CSP during BA and reliability stress conditions are evaluated.


IEEE Transactions on Components, Packaging and Manufacturing Technology | 2011

Interface Formation Between Metal and Polyimide in High Wiring Density Build-up Substrate

Kimihiro Yamanaka; Hidetoshi Yugawa; Masaaki Harazono; Yoshihiro Hosoi; Masahiro Fukui; Norihiro Inagaki

A key to a high-wiring-density build-up substrate is fine circuitry formation technology to satisfy the ever-increasing demands for miniaturization of electronics products. The surface roughness of a dielectric layer needs to be in the submicrometer scale for fine circuitry such as a line less than 10 μm wide. However, the Cu to dielectric adhesion strength of such a line would not be sufficient to prevent peeling off during manufacture and after heat treatment. Consequently, it is essential to have good adhesion between Cu and dielectric layer with chemical bonds between the metal and the dielectric layer. A polyimide film was introduced as a dielectric layer in a build-up substrate. Argon plasma-modified polyimide surfaces were sputtered with NiCr and then subjected to Cu electroplating. While unmodified polyimide had a weak adhesion strength of 0.12 kN m-1, Ar plasma-modified polyimide showed good adhesion strength of more than 0.5 kN m-1 even after 10 days of heat treatment at 172°C. X-ray photoelectron spectroscopy studies revealed that the adhesion strength was attributable to chemical bonds between Cr and the polyimide. Ar plasma-treated polyimide produced a large quantity of oxygen functional groups containing C=O bonds on the surface of polyimide, and subsequent NiCr sputtering produced C-O-Cr or C=O⋯Cr bonds to the polyimide. In addition, NiCr sputtering also attacked some of N-C=O and N-C bonds, and modified them to produce C-N-Cr or C-N⋯Cr bonds to the polyimide. These two types of mechanism produced sufficiently high Cu to polyimide adhesion to achieve fine line circuitry.


Archive | 2011

CIRCUIT BOARD AND MOUNTING STRUCTURE USING THE SAME

Masaaki Harazono; Yoshihiro Hosoi


Archive | 1996

Package for housing a photosemiconductor device

Masaaki Harazono


Archive | 2011

Method and apparatus for manufacturing prepreg sheet and prepreg sheet

Masaaki Harazono; Toshihiro Matsumoto


Archive | 2008

Fiber-reinforced resin and method for manufacturing the same

Masaaki Harazono; Masaharu Shirai; Katsura Hayashi


Archive | 2012

Printed circuit board, mount structure thereof, and methods of producing these

Masaaki Harazono; Yoshihiro Hosoi


Archive | 2010

Prepreg for printed wiring board and printed wiring board

Tooru Kitagawa; Kohei Kiriyama; Seiji Watanuki; Masaaki Harazono; Tadashi Nagasawa


International Symposium on Microelectronics | 2014

Thermal and Reliability Demonstration of a Large Die on a Low CTE Chip Scale Package

Tomoyuki Yamada; Masahiro Fukui; Kenji Terada; Masaaki Harazono; Teruya Fujisaki; Sushumna Iruvanti; Charles Carey; Yi Pan; Charlie Reynolds; Kamal K. Sikka; Brian Sundlof; Hilton T. Toy; Rebecca N. Wagner


International Symposium on Microelectronics | 2013

Organic Chip Scale Package (CSP) Development for Flip Chip Applications

Tomoyuki Yamada; Masahiro Fukui; Kenji Terada; Masaaki Harazono; Teruya Fujisaki; Charles L. Reynolds; Jean Audet; Yi Pan; Scott Preston Moore; Sushumna Iruvanti; Hsichang Liu; Hongqing Zhang; Brian Sundlof

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