Katsura Hayashi

High-speed machining of Inconel 718 with ceramic tools

Summary High speed machining for Inconel 718 was carried out with SiC whisker reinforced alumina, silicon nitride and TiC added alumina ceramic tools. In this test, not only the commercial available inserts, square type 120408 or button type 120400, but also specially designed cutting edges were tried. The SiC whisker tool showed the best performance in respect of notch wear at the cutting speed of under 300m/min. However, when the speed exceed -400m/min., the TiC added alumina ceramic tool showed the smallest wear compare to other tools. Specially designed cutting edge made the notch wear small.

Cutting Performance and Wear Characteristics of an Alumina-Zirconia Ceramic Tool in High-speed Face Milling

Summary High speed face milling for plain carbon steel S45C was carried out with ceramic tools. Pure alumina. T/C added alumina, and Zirconia toughened alumina ceramic tools were mainly used. Among the tested ceramic tools, the zirconia toughened alumina ceramic tool! showed the largest crater wear resistance in high speed face billing. However, in turning the same steel, the crater wear resistance of the ceramic tool was almost the same degree as compared to the other ceramic tools. The superior wear resistance of the zirconia toughered alumina ceramic tool is based on its stability for the reaction to Fe0 at high temperature.

Materials, Processes, and Performance of High-Wiring Density Buildup Substrate With Ultralow-Coefficient of Thermal Expansion

Flip-chip bonding on organic sequential buildup substrate technology has been an essential part of semiconductor packaging. In the quest for an ever higher semiconductor performance, there has been a rapidly increasing need for a finer pitch area array of flip-chip joints. However, the pitch has been limited by packaging technology. An advanced buildup substrate for fine pitch flip-chip bonding has been developed to satisfy the requirements for the most advanced semiconductor devices. The advanced substrate features a low-coefficient of thermal expansion (CTE) of 3 ppm°C, a fine pattern of 8 μm in line width and spacing, micro-vias of 25 μm in diameter, and plated through-holes of 100 μm in pitch. These features accommodate the density of a chip I/O of 104 cm-2, which is about ten times greater than that achieved in current organic packaging, and enable significant size reduction of semiconductor chips and the associated packages. The low-CTE significantly reduces the strain in the solder joints during the reflow process and ensures the solder joint reliability. This paper describes recent progress in the development of the advanced substrate technology as well as the technical difficulties.

Advanced Surface Laminar Circuit Packaging with low Coefficient of Thermal Expansion and high wiring density

Flip-chip bonding on organic sequential build-up substrate technology has been an essential part of semiconductor packaging. In the quest for an ever higher semiconductor performance there has been a rapid increasing need for a finer pitch area array flip-chip joints. However, the pitch has been limited by the packaging technology. Advanced Surface Laminar Circuit (Adv-SLC) packaging technology has been developed to satisfy the requirements for the most advanced semiconductor devices. Adv-SLC is a build-up substrate featuring a low Coefficient of Thermal Expansion (CTE) of 3 ppm/°C, a fine pattern of 8 µm in line width and spacing, plated through-holes of 100 µm in pitch and micro-vias of 25 °m in diameter. These features accommodate the density of a chip I/O of 104 cm−2, which is about ten times greater than that achieved in current organic packaging, and enables significant size reduction of semiconductor chips and the associated packages. The low CTE significantly reduces the strain in the solder joints during the reflow process and ensures the solder joint reliability. The CTE can be expanded to 5 ppm/°C by adjusting the volume ratio of the resin in the core. This paper describes recent progress in the development of Adv-SLC packaging technology.

Advanced Surface Laminar Circuit using new composite materials

This paper introduces a newly developed Advanced Surface Laminar Circuit (Adv-SLC) packaging technology, which utilizes new composite materials. Adv-SLC is a buildup substrate technology designed to satisfy the requirements of the most advanced semiconductor chips. We have developed a new dielectric material that is a build-up layer composed of two different materials. We also used a new material for the core substrate composed of Liquid Crystalline Polymer (LCP) reinforced with glass cloth. The new build-up layer has the following reliable properties: it can maintain both conductivity and dielectricity under the conditions of both a line/space width of 10/10μm and a via diameter of 30μm. The new core substrate also has excellent reliable properties as follows: it can maintain both conductivity and dielectricity under the condition of both a through hole diameter of 60μm and a through hole pitch of 120μm. We were able to confirm that the formation of the new substrate with the aforementioned new design rules contributes to reduce the silicon chip size. Consequently, due to all of the aforementioned properties, Adv-SLC contributes to reduce thermal stress when we mount a flip chip.

Advanced Surface Laminar Circuits Using Newly Developed Resins

This paper introduces a newly developed advanced surface laminar circuit (Adv-SLC) packaging technology, which utilizes new composite materials. Adv-SLC is a build-up substrate technology designed to fulfill the requirements of the most advanced semiconductor chips. Our new dielectric material is a build-up layer composed of two different materials. We also used a new material for the core substrate, composed of liquid crystalline polymer reinforced with glass cloth. The build-up layer has the following, highly reliable properties: it can maintain both conductivity and dielectricity under the conditions of both a line/space width of 10/10 μm and a via diameter of 30 μm . The core substrate also has excellent, reliable properties: it can maintain both conductivity and dielectricity under the conditions of a through hole diameter of 60 μm and a through hole pitch of 120 μm. We were able to confirm that the formation of the new substrate with the aforementioned new design rules contributes to reduce the size of the silicon chip. Consequently, Adv-SLC contributes to reduce thermal stress when mounting a flip chip.

Suppression of tool wear by using an inert gas in face milling

Abstract In order to reduce crater wear and thermal cracks of cutting tool in high speed face milling of plain carbon steels, an inert gas, which flowed through a spindle of a milling machine, was used. Nitrogen gas was supplied through spindle to the cutting edge so that the cutting edge would not be oxidized. The effects of the nitrogen gas on the tool failure were influenced by shape of the nozzle and velocity of the gas from the nozzle. Under the good conditions, crater wear of the carbide tool P10 was reduced by 50% compared to cutting in the air.

Nano-Silica Composite Laminate

This paper introduces a newly-developed Nano-Silica Composite Laminate packaging technology that utilizes a nano-silica matrix composite material with outstanding properties. Nano-Silica Composite Laminate packaging technology enables us to create a thinner, downsized packaging that is less susceptible to warpage. In order to verify the advantageous properties of Nano-Silica Composite Laminate, we measured the degree of warpage by utilizing a dielectric test substrate that was composed of Nano-Silica Composite Laminate and resin films. The results obtained in this study demonstrated that the dielectric material created using Nano-Silica Composite Laminate allows us to avoid the resins undesirable tendency of allowing the coefficient of thermal expansion (CTE) to increase when the temperature rises beyond the glass transition temperature. The storage modulus of Nano-Silica Composite Laminate showed 30 GPa, which is more than five times higher than that of ordinary resin. Therefore, we were able to confirm that using Nano-Silica Composite Laminate contributes to decreasing warpage of the conventional substrate during the packaging process. Furthermore, we confirmed that the test substrate has the following extremely reliable properties: it can maintain both conductivity and dielectricity under the conditions of both a line/space width of 10/10μm and a via diameter of 30 μm. Consequently, through the test results it has been confirmed that Nano-Silica Composite Laminate is one of the most appropriate substrates available to strengthen the interconnection between a silicon chip and substrate, and to protect the large-scale integrated (LSI) circuits from breaking.

High Speed Face Milling of Plain Carbon Steel with Alumina-Zirconia Ceramic Tool.

High speed face milling for plain carbon steel S 45 C was carried out with ceramic tools. TiC added alumina, and zirconia toughened alumina ceramic tools were mainly used. Among the tested ceramic tools, the zirconia toughened alumina ceramic tool showed the largest crater wear resistance in high speed face milling. However, in turning the same steel, the crater wear resistance of the ceramic tool was almost the same degree as compared to the other ceramic tools. The superior wear resistance of the zirconia toughened alumina ceramic tool is based on its stability for the reaction with Fe0 at high temperature.