Masaharu Imai

Rapid prototyping of JPEG encoder using the ASIP development system: PEAS-III

In this paper, the JPEG encoder application, one of the DSP applications, was implemented using the ASIP development system: PEAS-III. Instructions for the JPEG encoder, such as DCT instruction, and butterfly instructions, were added to the initial design. Area, performance, and execution cycles of the processors were calculated using the generated HDL description, compiler, and assembler by PEAS-III. From the experimental results, 12 architectures can be designed in 160 hours, and the designer can select an optimal architecture that satisfies design constraints considering the hardware cost, clock frequency and execution cycles.

VLSI implementation of fractal image compression processor for moving pictures

This paper proposes an efficient VLSI architecture of fractal image coding for moving pictures. The proposed processor makes use of parallel searching for similar domain blocks by grouping range blocks by identical classes. Furthermore, to encode a moving picture at high-speed, utilizing the domain block information obtained in the coding of a previous frame to code the following frame is employed. According to this architecture, a smaller fractal image coding VLSI can be realized. The architecture is capable of high-speed, real-time encoding not only for still images but also for full-motion pictures using a circuit size. The compression ratios are 2-5 times higher, and the code processing time is 10 times faster than those of conventional fractal techniques. The adoption of the proposed VLSI architecture technique achieves real-time encoding of full-motion videos, and the circuit size of VLSI is much smaller than previously proposed fractal processors.

Chapter 7 – ASIP Meister

Publisher Summary nThis chapter focuses on application-specific instruction-set processor (ASIP) Meister, which is a design environment that provides designers with an interactive environment to specify, design, and generate an ASIP and possibly legacy off-the-shelf processor cores based on excellent implementation methodology. ASIP Meister generates an HDL description of a target ASIP and various application program development tools such as assemblers, compilers, and instruction-set simulators. ASIP Meister supports a flexible pipeline model where fetch or decode stages are changed with execution stages whose modification is usually supported by architecture description languages (ADLs). This allows the designers to explore the design space in a short time, thus remarkably improving the design productivity of ASIPs. ASIP Meister supports various architecture parameters as it has variable numbers of pipeline stages, parameterized hardware resources instantiated from a flexible hardware model-database management system (FHM-DBMS), supports multicycle instructions and delayed branches, and handles external and internal interrupts. The FHM-DBMS is utilized in the framework to obtain an instance of resources from the FHM database and it can estimate the design quality such as area, delay, and power consumption of the target processor in an early stage of design. Designers can also input and change architecture parameters by using a graphical user interface (GUI) and the datapath, and control logic of ASIP can be automatically generated from the architectural parameters and microoperation description of instructions. Many academic research groups have used ASIP Meister for implementing and confirming their state-of-the-art architecture and it has been adopted by many universities as an education tool in teaching and lab classes.