Keishi Sakanushi

The quarter-state-sequence floorplan representation

A floorplan of a bounding box is its dissection into rectangles (rooms) by horizontal and vertical segments. This paper proposes a string data structure called the Quarter-state sequence (or Q sequence) to represent the floorplan. The Q sequence is a concatenation of the states of rooms along the Abe order and is related to the VH graph, which is the union of the vertical-constraint and horizontal-constraint graphs. It is proved that any floorplan of n rooms is uniquely encoded by a Q sequence and any Q sequence is uniquely decoded to a floorplan, both in O(n) time. An exact formula for counting distinct floorplans is given and compared with existing bounds. A linear time transformation of one Q sequence to another is defined. An n-room packing algorithm based on simulated annealing was implemented and found to compare favorably with existing packing algorithms.

RTK-Spec TRON: A Simulation Model of an ITRON Based RTOS Kernel in SystemC

The paper presents the methodology and the modeling constructs we have developed to capture the real time aspects of RTOS (real time operating system) simulation models in a system level design language (SLDL) like SystemC. We describe these constructs and show how they are used to build a simulation model of an RTOS kernel targeting the /spl mu/-ITRON (micro industrial TRON - the real time operating system nucleus) OS specification standard.

A high performance algorithm for scheduling and hardware-software partitioning on MPSoCs

Multi-processor system-on-chip (MPSoC) is an integrated circuit containing multiple cores that implements most of the functionality of a complex electronic system and some other components like FPGA/ASIC on single chip. The most crucial things in such like these systems are the performance, energy, power and area optimization. Moreover, scheduling the tasks of an application on to the processors (cores) and HW/SW partitioning are inter-dependent in the traditional design space exploration process. In this paper, we propose an algorithm to produce the optimality of scheduling and optimize the number of cores that can be used and also reduce the overall execution time and number of buses on the chip by using efficient hardwaresoftware co-design partitioning technique. The viability and potential of the proposed algorithm is demonstrated by extensive experimental results to conclude that the proposed algorithm is an efficient scheme to obtain the optimality of scheduling and partitioning with hard and large task graph problems.

Electronic triage system for continuously monitoring casualties at disaster scenes

Unfortunately, many persons are injured or killed during disasters. The problems of paper triage tags, which are widely used at disaster scenes, include an inability to show the current priorities of casualties and a failure to collect the physiological conditions of the casualties. To save lives, this paper proposes an electronic triage system that consists of two types of electronic triage tags and an electronic triage server. The electronic triage tag continuously monitors the vital signs of casualties and transmits them to the electronic triage server, and the electronic triage system shows the current priorities of the casualties. Experimental results show that our proposed electronic triage system can save more lives than paper triage tags.

A Processor Generation Method from Instruction Behavior Description Based on Specification of Pipeline Stages and Functional Units

This paper proposes a method for generating a pipeline processor from the behavior description of instructions. In the proposed method, a micro-operation description is generated by complementing the behavior description with specifications of the pipeline stages, such as the number of pipeline stages, the attributes of each stage. From the behavior description, software development tools, such as an instruction-set simulator (ISS), a compiler, and an assembler can be generated, and a synthesizable HDL description of a processor can be generated from the micro-operation description. Compared with the conventional method of writing individual descriptions, the proposed method can dramatically reduce the code size of the architectural description language and the design time without degrading the design quality. As a result, a design space exploration can be performed efficiently.

Automated architecture exploration for low energy reconfigurable AGU

In this paper, we introduce automated architecture exploration challenge of reconfigurable AGU (Address Generation Unit) based on coarse grained reconfigurable architecture for effective address calculation. To use reconfigurable AGU effectively, it is important to specify its architecture from many architecture candidates. Introduced architecture exploration method enables to explore the vast solution space effectively, and we can obtain the optimal trade-off points about 164 times faster than the exhaustive search.

Synthesizable HDL generation method for configurable VLIW processors

This paper proposes a synthesizable HDL code generation method using a processor specification description. The proposed approach can change the number of slots and pipeline stages, and dispatching rule to assign operations to resources. In addition, designers can specify each instruction behavior using the specification language. A control logic, a decode logic, and a data path of VLIW processor are generated from the processor specification. Designers can explore ASIP design space using the proposed a p proach effectively, because the amount of description and the modification cost are small. Using this approach, it took about eight hours to design 36 VLIW processors. Moreover, this approach provides a 82% reduction on the average compared to the description of the HDL code.

Generation of application-domain Specific Instruction-set Processors

This paper introduces a generation method of Application-domain Specific Instruction-set Processors (ASIP) and shows an design example. ASIP is a processor which has some extended instructions specific to application domain. First, advantage of ASIC is explained. Then, some processor generation approaches explained, and an ASIP development environment called ASIP Meister is introduced. Finally, design example shows some effectiveness of ASIP.

Enabling RTOS simulation modeling in a system level design language

In this paper, we propose a new process definition (T-THREAD) and an extension to the existing SystemC simulation engine (SIM_API library) to capture the real time aspects of RTOS simulation models in an SLDL like SystemC. We describe the execution semantics of this process and show how it works in a complete embedded system simulation model.

Architecture-level performance estimation for IP-based embedded systems

In this paper, we propose a architecture-level performance estimation method for IP-based embedded systems using system-level profiling. Our method enables the performance estimation by the following procedures: 1) System-level profiling. 2) Automatic construction of the execution dependency graph (EDG) from the profile information. 3) Estimation of the system performance based on the EDG analysis. Our method enables fast performance estimation because it can estimate the performance of various architectures from the same system-level profile information. Experimental results show that our estimation method is about 10,000 times faster than the architecture-level simulations.