Masaharu Ninomiya

Highly strain-relaxed ultrathin SiGe-on-insulator structure by Ge condensation process combined with H+ irradiation and postannealing

Strain-relaxation process of SiGe-on-insulator (SGOI) structures in the oxidation induced Ge condensation method has been investigated as a function of the SiGe thickness. Complete relaxation was obtained for thick SGOI layers (>100nm). However, the relaxation rates abruptly decreased with decreasing SiGe thickness below 50nm, i.e., the relaxation rate of 30% at 30nm SiGe thickness. In order to improve this phenomenon, a method combined with H+ irradiation with a medium dose (5×1015cm−2) and postannealing (1200°C) has been developed. This successfully achieved the high relaxation rate (70%) in the ultrathin SGOI (30nm).

Enhanced stress relaxation in ultrathin SiGe-on-insulator by H+-implantation-assisted oxidation

Effects of H+ implantation (⩽5×1016cm−2) on stress relaxation in an oxidation-induced Ge condensation method have been investigated to form stress-relaxed ultrathin (∼30nm) SiGe-on-insulator (SGOI) virtual substrates. High-dose (⩾1015cm−2) implantation enhanced stress relaxation, which was attributed to bond breaking at the SiGe∕buriedSiO2 interface. However, oxidation velocity was also enhanced due to irradiation defects. Two-step annealing (500 °C for 30 min and 850 °C for 60 min) before oxidation was proposed to remove irradiation defects. This achieved enhanced stress relaxation in ultrathin SGOI without changing oxidation velocity.

Electrical characterization of strained Si∕SiGe wafers using transient capacitance measurements

Interface states density (Nss) and minority carrier generation lifetime (τg) were evaluated for strained Si(St-Si)∕SiGe wafers using deep level transient spectroscopy and metal-oxide-semiconductor transient capacitance methods. Nss shows an independence on St-Si thickness (dSi) and an obvious dependence on Ge fraction (Ge%). τg shows a strong dependence on both dSi and Ge%. The reasons of these dependencies are discussed in detail.

Characterization of mirror-polished silicon wafers by Makyoh method

Abstract Makyoh, the “Magic Mirror” is a very useful tool with which to visualize local irregularities of the surface of a mirror-like polished silicon wafer. Using the Makyoh method, bright and dark spots are visible in the image of wafers projected on an instrument screen. However, these spots have not yet been correlated to specific defects on a wafer surface. First, local convex-type defects on the mirror-like surface of silicon wafers are observed with Makyoh, a flatness tester and other micro surface measurement systems. Next, we report our attempts to create actrual convex and concave shapes on silicon wafer surfaces by intentionally varying polishing conditions, and which shapes are observed. We also discuss the relationship between silicon wafer flatness and the Makyoh magic mirror image.

Improvement of Oxidation-Induced Ge Condensation Method by H+ Implantation and Two-Step Annealing for Highly Stress-Relaxed SiGe-on-Insulator

The effects of the H+ implantation (8.1 keV and 0–5×1016 cm-2) and two-step annealing (1st: 500°C for 30 min, 2nd: 850°C for 60 min) on the stress relaxation of c-Si1-xGex buffer layers on insulator (SGOI) formed by the oxidation-induced Ge condensation process have been investigated. The stress relaxation of SGOI during oxidation (1100°C) was significantly improved by high-dose (>1015 cm-2) H+ implantation. However, the oxidation was also enhanced by the implantation. The enhanced oxidation was completely suppressed by the two-step annealing before oxidation. The enhanced stress relaxation was attributed to the enhanced gliding of the c-Si1-xGex layers on SiO2. This newly developed combination method of H+ implantation, the two-step annealing, and the oxidation-induced Ge condensation will be a powerful tool in the fabrication of highly relaxed SGOI for growth of strained Si layers.

Data compaction method for raster–scan exposure system

A data compaction method and a data processing system developed for raster–scan exposure system are presented. The purpose of the method is to enhance flexibility in pattern size and to increase writing speed of a raster–scan system. The data format for compaction and the data transmission scheme are given. The encoding and decoding procedures are described. Data quantity of advanced LSI patterns is examined and it is shown that data compaction ratio of 1/7 to 1/70 is attained. Writing speed of 40 MHz is also achieved. By this method, reticle pattern as large as 105×105 dots and composite patterns are successfully delineated.

An Electron Beam Exposure System (VL-R1)

The system design and performance of a newly developed electron beam exposure system are reported. The basic operation is of a raster scan over a narrow field with a continuously moving stage. The system is capable of practical making of master masks and reticles including composite patterns. A pattern size as large as 105×105 dots is managed by a data compaction method and by a continuous data flow method from a magnetic disk to a DMA. LSI patterns of 2 µm geometry are delineated at a speed of 2 cm2/min. The electron charge density as high as 15 µC/cm2 at 20 kV was achieved.

Evaluation of Interface States Density and Minority Carrier Generation Lifetime for Strained Si/SiGe Wafers Using Transient Capacitance Method

Interface states density (Nss) and minority carrier generation lifetime (?g) were evaluated in detail for strained Si/SiGe wafers by deep-level transient spectroscopy and metal-oxide-semiconductor transient capacitance methods. Nss shows a nondependence on strained Si thickness (dSi) within a critical thickness and a clear dependence on Ge fraction (Ge%). ?g shows a strong dependence on both dSi and Ge%. The reasons for these dependences are discussed in detail.

Improved Oxidation-Induced Ge Condensation Technique Using H+ Implantation and Post Annealing for Highly Stress-Relaxed Ultrathin SiGe on Insulator

The oxidation-induced Ge condensation of SiGe/Si-on-insulator structures was investigated. The relaxation rate of SiGe on insulator (SGOI) abruptly decreased with SiGe thickness below 50 nm. To enhance the relaxation rate in ultra thin SGOI, a new technique combined with intermediate-dose H+ implantation (5×1015 cm-2) and post annealing (1200 °C) was developed. It was demonstrated that highly relaxed (70%) ultra thin SGOI with a low defect density (<106 cm-2) is realized by this technique.

Evaluation of interface states and minority carrier generation lifetime for strained Si/SiGe wafers using transient capacitance method

Interface states intensity (Nss) and minority carrier generation lifetime (/spl tau//sub g/) were evaluated for strained Si (St-Si)/SiGe wafers using deep level transient spectroscopy (DLTS) and metal-oxide-semiconductor (MOS) transient capacitance (C-t) methods. The dependences of Nss and /spl tau//sub g/ on St-Si thickness (d/sub Si/) and Ge fraction (Ge%) were shown clearly. By the same gate film fabrication and electrical measurements for a bulk Si MOS, the values of Nss and /spl tau//sub g/ of St-Si MOS are similar to those of bulk Si MOS, showing good wafer quality.