Masahide Tadokoro

Improvement of gate CD uniformity for 55 nm node logic devices

This paper examines improvement in post-etching gate critical dimension (CD) uniformity by post exposure bake (PEB) temperature control. Although intra-wafer and inter-wafer resist CD uniformity is improved by PEB temperature optimization, intra-wafer gate CD uniformity after etching could not be improved due to etcher-attributed factors. To improve these factors, we carried out two-step optimization that combines lithography CD optimization with etching CD optimization. By using this method, the optimization strategy can clarify the targets of optimization in each step. PEB temperature optimization was performed by two step optimization in which etcher-attributed CD variations were canceled out, leading to 66% improvement of gate etching CD uniformity successfully. Without any changes in modification parameter, this PEB temperature optimization proved to be applicable to several reticle patterns with different pattern density. Moreover, this optimization method proved the applicability to the gate process for a 55nm node logic device for the duration of five months without modification. The result proved its long-term stability and practicality.

Effects produced by CDU improvement of resist pattern with PEB temperature control for wiring resistance variation reduction

Semiconductor manufacturing technology has shifted towards finer design rules, and demands for critical dimension uniformity (CDU) of resist patterns have become greater than ever. One of the methods for improving CDU of resist pattern is to control the temperature of post-exposure bake (PEB). When ArF resist is used, there is a certain relationship between critical dimension (CD) and PEB temperature. By utilizing this relationship, Resist Pattern CDU can be improved through control of within-wafer temperature distribution in the PEB process. We have already applied this method to Resist Pattern CDU improvement and have achieved these results. In this evaluation, we aim at: 1. Clarifying the relationship between the improvement in Resist Pattern CDU through PEB temperature control and the improvement in Etching Pattern CDU. 2. Verifying whether Resist Pattern CDU improvement through PEB temperature control has any effect on the reduction in wiring resistance variation. The evaluation procedure is: 1. Preparation of wafers with base film of doped Poly-Si (D-Poly). 2. Creation of two sets of samples on the base, a set of samples with good Resist Pattern CDU and a set of samples with poor Resist Pattern CDU. 3. Etching of the two sets under the same conditions. 4. Measurements of CD and wiring resistance. We used Optical CD Measurement (OCD) for measurement of resist pattern and etching pattern for the reason that OCD is minimally affected by Line Edge Roughness (LER). As a result, we found that; 1. The improvement in Resist Pattern CDU leads to the improvement in Etching Pattern CDU . 2. The improvement in Resist Pattern CDU has an effect on the reduction in wiring resistance variation. There is a cause-and-effect relationship between wiring resistance variation and transistor characteristics. From this relationship, we expect that the improvement in Resist Pattern CDU through PEB temperature control can contribute to device performance improvement.

CDU improvement technology of etching pattern using photo lithography

Semiconductor manufacturing technology has shifted towards finer design rules, and demands for critical dimension uniformity (CDU) of resist patterns have become greater than ever. One of the methods for improving Resist Pattern CDU is to control post-exposure bake (PEB) temperature. When ArF resist is used, there is a certain relationship between critical dimension (CD) and PEB temperature. By utilizing this relationship, Resist Pattern CDU can be improved through control of within-wafer temperature distribution in the PEB process. Resist Pattern CDU improvement contributes to Etching Pattern CDU improvement to a certain degree. To further improve Etching Pattern CDU, etcher-specific CD variation needs to be controlled. In this evaluation, 1. We verified whether etcher-specific CD variation can be controlled and consequently Etching Pattern CDU can be further improved by controlling resist patterns through PEB control. 2. Verifying whether Etching Pattern CDU improvement through has any effect on the reduction in wiring resistance variation. The evaluation procedure is as follows.1. Wafers with base film of Doped Poly-Si (D-Poly) were prepared. 2. Resist patterns were created on them. 3. To determine etcher-specific characteristics, the first etching was performed, and after cleaning off the resist and BARC, CD of etched D-Poly was measured. 4. Using the obtained within-wafer CD distribution of the etching patterns, within-wafer temperature distribution in the PEB process was modified. 5. Resist patterns were created again, followed by the second etching and cleaning, which was followed by CD measurement. We used Optical CD Measurement (OCD) for measurement of resist patterns and etching patterns as OCD is minimally affected by Line Edge Roughness (LER). As a result, 1. We confirmed the effect of Resist Pattern CD control through PEB control on the reduction in etcher-specific CD variation and the improvement in Etching Pattern CDU. 2. The improvement in Etching Pattern CDU has an effect on the reduction in wiring resistance variation. The method for Etching Pattern CDU improvement through PEB control reduces within-wafer variation of MOS transistors gate length. Therefore, with this method, we can expect to observe uniform within-wafer MOS transistor characteristics.