Masaki Satake

Compensation for EUV multilayer defects within arbitrary layouts by absorber pattern modification

According to the ITRS roadmap, mask defects are among the top technical challenges to introduction of extreme ultraviolet (EUV) lithography into production. Making a multilayer defect-free extreme ultraviolet (EUV) blank is not possible today, and is unlikely to happen in the next few years. This means that EUV must work with multilayer defects present on the mask. The method proposed by Luminescent is to compensate effects of multilayer defects on images by modifying the absorber patterns. The effect of a multilayer defect is to distort the images of adjacent absorber patterns. Although the defect cannot be repaired, the images may be restored to their desired targets by changing the absorber patterns. This method was introduced in our paper at BACUS 2010, which described a simple pixel-based compensation algorithm using a fast multilayer model. The fast model made it possible to complete the compensation calculations in seconds, instead of days or weeks required for rigorous Finite Domain Time Difference (FDTD) simulations. In this paper the method is extended from one-dimensional to two-dimensional patterns by formulating the problem with level-set methods. Since only the top layer profile is measurable a multi-layer growth model is applied to infer the location of the defect and how it distorts the multi-layer reflector. The fast image model is applied to determine how these assumptions influence accuracy of the compensation method.

EUV mask multilayer defects and their printability under different multilayer deposition conditions

Extreme ultraviolet (EUV) patterning appears feasible using currently available EUV exposure tools, but some issues must still be resolved for EUV patterning to be used in production. Defects in EUV mask blanks are one such major issue and inspection tools are needed to detect phase defects on EUV mask blanks that could possibly print on the wafer. Currently available inspection tools can capture defects on the mask, but they also need to be able to classify possible printable defects. Defect classification for repair and mitigation of printable defects is very difficult using deep ultraviolet (DUV) inspection tools; however, if the actinic inspection tool (AIT) could gather defect information from more multilayer (ML) stacks, it may be able to separate printable defects from unprintable defects. If unprintable defects could be eliminated, the defect information could be used for mask pattern shifts to reduce printable defects. Fewer defects would need to be repaired if there were a better chance of capturing printable defects using an actinic inspection tool. Being able to detect printable defects on EUV blanks is therefore critical in mask making. In this paper, we describe the characterization of programmed ML phase defects in the manufacturing of EUV mask blanks using the state-of-the-art mask metrology equipment in SEMATECHs Mask Blank Development Center (MBDC). Programmed defects of various dimensions were prepared using e-beam patterning technology and Mo/Si MLs were deposited with SEMATECHs best known method (BKM) and pit smoothing conditions on programmed defects to characterize ML phase defects. Atomic force microscopy (AFM) and transmission electron microscopy (TEM) were used to study ML profile changes, while SEMATECHs AIT was used to image ML phase defects and predict their printability. Multilayer defect reconstruction (MDR) was done using AFM images, which were then compared to TEM images. Defect printability simulation (DPS) was used for comparison to AIT through-focus images. 22 nm, 27 nm, and 32 nm line and space (L/S) absorber patterns were positioned on top of programmed ML phase defects and simulated defect printability. The ML phase defects are located at the edge of L/S patterns and at the center of space patterns and Bossung plot was used to separate printable defects from unprintable defects.

Computational metrology and inspection (CMI) in mask inspection, metrology, review, and repair

Abstract Mask manufacturers will be impacted by two significant technology requirements at 22 nm and below: the first is the more extensive use of resolution enhancement technologies (RET), such as aggressive optical proximity correction (OPC), inverse lithography technology (ILT), and source mask optimization (SMO); the second is the extreme ultraviolet (EUV) technology. Both will create difficulties for mask inspection, defect disposition, metrology, review, and repair. For example, the use of ILT and SMO significantly increases mask complexity, making mask defect disposition more challenging than ever. The EUV actinic inspection and AIMS™ will not be available for at least a few years, which make the EUV defect inspection and disposition more difficult, particularly regarding multilayer defects. Computational metrology and inspection (CMI), which has broad applications in mask inspection, metrology, review, and repair, has become essential to fill this technology gap. In this paper, several such CMI applications are presented and discussed.

Patterning strategy and performance of 1.3NA tool for 32nm node lithography

We have designed the lithography process for 32nm node logic devices under the 1.3NA single exposure conditions. The simulation and experimental results indicate that the minimum pitches should be determined as 100nm for line pattern and 120nm for contact hole pattern, respectively. The isolated feature needs SRAF to pull up the DOF margin. High density SRAM cell with 0.15um2 area is clearly resolved across exposure and focus window. The 1.3NA scanner has sufficient focus and overlay stability. There is no immersion induced defects.

A fast approach to model EUV mask 3D and shadowing effects

EUV lithography is one of the leading candidates to replace traditional DUV for semiconductor patterning. Different from DUV mask, EUV masks consists of an absorber pattern layer and 40 layers of alternating molybdenum and silicon to generate reflective mask near field. Due to the complexity of the EUV mask structure, the high profile of the absorber layer relative to wavelength, and the non-telecentric nature of EUV optics, mask 3D- and shadowing effects are important and must be taken into consideration. The goal of our simulator is to build an empirical model specially tailored to capture such effects by reconstructing thin mask spectrum to match with rigorous simulation within the pupil of interests. In this study, we will present the mechanisms and accuracy results of our absorber model.

AIMS D2DB simulation for DUV and EUV mask inspection

AIMS™ Die-to-Die (D2D) is widely used in checking the wafer printability of mask defects for DUV lithography. Two AIMS images, a reference and a defect image, are captured and compared with differences larger than certain tolerances identified as real defects. Since two AIMS images are needed, and since AIMS system time is precious, it is desirable to save image search and capture time by simulating reference images from the OPC mask pattern and AIMS optics. This approach is called Die-to-Database (D2DB). Another reason that D2DB is desirable is in single die mask, where the reference image from another die does not exist. This paper presents our approach to simulate AIMS optics and mask 3D effects. Unlike OPC model, whose major concern is predicting printed CD, AIMS D2DB model must produce simulated images that match measured images across the image field. This requires a careful modeling of all effects that impact the final image quality. We present a vector-diffraction theory that is based on solid theoretical foundations and a general formulation of mask model that are applicable to both rigorous Maxwell solver and empirical model that can capture the mask 3D-effects. We demonstrated the validity of our approach by comparing our simulated image with AIMS machine measured images. We also briefly discuss the necessary changes needed to model EUV optics. Simulation is particularly useful while the industry waits for an actinic EUV-AIMS tool.

Patterning performance of hyper NA immersion lithography for 32nm node logic process

We have developed the lithography process for 32nm node logic devices under the 1.35NA single-exposure conditions. In low-k1 generation, we have to consider the minimum pitch resolution and two-dimensional pattern fidelity at the same time. Although strong RET (Resonance Enhancement Technique) can achieve the high image contrast, it has negative effects like line end shortening and resist pattern collapse. Moderate RET such as annular illumination can combine the minimum pitch resolution and two-dimensional pattern fidelity with hyper NA illumination condition. The simulation and experimental results indicate that the minimum pitches should be determined as 100nm for line pattern and 110nm for contact hole pattern, respectively. The isolated contact hole needs SRAF and focus drift exposure to improve DOF. Embedded SRAM cell of 0.125&mgr;m2 area is clearly resolved across exposure and focus window.

Statistical approach utilizing neural networks for CD error prediction

We studied a three-layer backpropagation neural network to describe nonlinear relationships between inputs (error sources/control knobs) and output CDs. The application of the neural network to modeling of optical proximity effect for a 65nm node CMOS gate layer was investigated. The prediction accuracy of the neural network was improved with the increase in the training data size, becoming higher than that of a conventional lithography simulation with a lumped parameter model. The result suggests that neural networks trained with a sufficient amount of data can provide the same or higher accuracy for the CD error prediction than physical model-based approaches. The use of information of aerial images as input parameters improved the accuracy. Also, pattern density effects, which are difficult to treat by a conventional lithography simulation, could be successfully reflected in the CD error prediction. Using lot data over a period of time, we trained a neural network in which the exposure parameters and lot mean CDs were inputs and outputs, respectively. From the network, lot mean CDs for successive periods were able to be predicted. From these results, we conclude that the application of neural networks for CD control in advanced lithography is worth developing.

Assessment of wafer pattern prediction accuracy by introducing effectively equivalent mask patterns

Mask topography effects arise important components of optical image formation at 45nm node and beyond for attenuated Phase Shift Mask (attPSM). Since calculation of mask topography effects based on rigorous model is very costly, it is unrealistic for Optical Proximity Correction (OPC) and lithography design. This paper investigates an approximation model that takes mask topography effects into consideration. We propose the concept of Effectively Equivalent Mask Patterns (EEMP) method to obtain approximated optical images which include mask topography effects. We found mask space width is the main factor among mask topography effects. For realizing the EEMP method, we introduce and evaluate two approximation methods for mask topography effects. One is the simple space model and the other is the Proximity Mask Opening (PMO) model, which is a model of waveguide effects. EEMP with PMO model can improve prediction accuracy at both 1-dimensional and 2-dimensional patterns and increase in run time for EEMP with PMO model is 40 percent of that required for thin film simulations.

Defect printability comparing actinic printing with advanced simulation for EUV masks

We describe the printability of native phase defects categorized by type and dimension using NXE3100 EUV scanner and DPS (Defect Printability Simulator) software developed by Luminescent Technologies. The critical dimension (CD) error on wafers simulated by the DPS is strongly affected by the geometry of the multilayer (ML) used as an input parameter for simulation. This finding is supported by cross section images of the ML acquired from transmission electron microscopy (TEM) showing that the diameter of the defect and geometry of the ML are closely related. Accordingly, the selection of the type of ML geometry seems to be important in the accuracy of defect printability simulation. The CD error simulated from the DPS using reconstructed ML geometry shows better correspondence with that measured on a wafer than conformal or smoothed ML geometry. The DPS software shows good simulation performance in predicting defect printability at 27nm HP node. This is verified by wafer printing and RCWA simulation.