Masanao Ise

An energy-efficient architecture of wireless home network based on MAC broadcast and transmission power control

To construct an energy-efficient wireless home network based on IEEE 802.15.4, a novel architecture is proposed. In this architecture, all nodes are classified into stationary nodes and mobile nodes according to the functionality of each node. Mobile nodes are usually battery-powered, and therefore need low-power operation. In order to improve power consumption of mobile nodes, effective handover sequence based on MAC broadcast and transmission power control based on LQ (link quality) are employed. Experimental results demonstrate that by using the proposed architecture, communication time and power consumption of mobile nodes can be reduced by 1.2 seconds and 42.8%, respectively.

Development of a real-time vital data collection system from players during a football game

In order to plan effective training menus and avoid injuries and diseases, vital signs monitoring for athletes during training and game is essential, where a key issue is how to collect vital data reliably and in real-time from many people spread in a large field. To realize such a real-time vital data monitoring system, we developed prototype wireless vital sensor nodes, and conducted twice field experiments to evaluate the packet success rate (PSR), where we put the sensor nodes to the waists of 22 players and collected packets from all of them during a football game. In this paper, we present the detail of the real-time vital data collection system composed of the prototype sensor nodes and data collection nodes, and discuss the experimental results in terms of PSR and diversity gain.

Elements of a real-time vital signs monitoring system for players during a football game

We have developed a real-time vital signs monitoring system for two years in 2012 and 2013. Just by putting a single vital sensor node to the back waist position of each player and placing four data collection nodes around a field, the system can monitor at a note PC heart rate (HR), energy expenditure (EE) and body temperature (BT) for all players during a football game in real-time, periodically and reliably. The system is based on novel vital sensing technique and wireless data transmission technique. This paper introduces the two techniques in the system, presents some problems encountered in the system development and discusses solutions for them.

Performance evaluation of packet forwarding methods in real-time vital data collection for players during a football game

Real-time vital data monitoring for athletes during training and game is essential for planning effective training menus and avoiding injuries and diseases. Especially for team sports such as footfall and rugby, how to reliably collect vital data from many players spread in a large field is a key issue. In our previous work [1], we developed a real-time vital data collection system in which a wireless sensor node attached at the waist position of each player broadcasts packets to data collection nodes placed around a football field. Our field experiments showed that, (1) for the 920 MHz band, the packet success rate can be almost 1.0 when using 3 or 4 data collection nodes, whereas for the 2.4 GHz band, the packet success rate is less than 0.85 even when using 6 data collection nodes, and (2) the suitable antenna height of the data collection node is 2 meters. In this paper, we discuss a suitable packet forwarding method from the data collection nodes to a sink node at a technical trainer or a coach. By field experiments, we compare the packet error rate between a single-hop packet forwarding in the 920 MHz band and a multi-hop packet forwarding in the 2.4 GHz band. Furthermore, we show some interesting events on the packet error rates for different player positions such as forward, midfielder, defender and goalkeeper.

Dependable embedded processor core for higher reliability

We are developing a 32bit embedded processor core with soft error detection and recovery mechanisms. Soft errors caused by atmospheric neutron hits or performance aging in an embedded processor core make the mission-critical embedded system to produce dangerous results like system failure. Our research goal is to investigate soft error rates in the proposed embedded processor core through fault injection tests using a neutron beam or an electromagnetic pulse generator.

VLSI architecture of digital matched filter and prime interleaver for W-CDMA

A VLSI architecture dedicated to W-CDMA (Wideband Code Division Multiple Access) baseband modem is described, with the main theme focused on the cell searcher and PIL (Prime InterLeaver). A search algorithm is refined for the cell searcher to minimize the circuit size, maintaining the operating throughput. In addition, a time-shared scheme is adopted for the turbo encoding/decoding, aiming at the maximization of the hardware sharing in the encoding/decoding process. Finally, implementation results are shown to demonstrate that the proposed architecture can contribute much toward the practical low-power implementation of W-CDMA baseband modem LSI.

System-on-a-chip architecture for W-CDMA baseband modem LSI

A system-on-a-chip architecture dedicated to a W-CDMA (Wideband Code Division Multiple Access) baseband modem LSI is described, with the main theme focused on the cell searcher and PIL (Prime InterLeaver) modules. First, the next generation wireless communication system based on W-CDMA is briefly overviewed. Then, a novel VLSI architecture is proposed mainly for the cell searcher and PIL modules, in which a search algorithm is refined for the cell searcher to minimize the circuit size, maintaining the operating throughput, and a time-shared scheme is adopted for the Turbo encoding/decoding, aiming at the maximization of the hardware sharing in the encoding/decoding process. Finally, implementation results are shown to demonstrate that the proposed architecture can contribute much toward the practical low-power implementation of a W-CDMA baseband modem LSI.

Probability of calculation failures by soft errors in an embedded processor core

We are developing a 32-bit embedded processor core with soft error detection and recovery mechanisms. Adding a parity bit into pipeline registers makes it possible to detect Single Event Upset in an processor core. Detection of 2-bit and less Multiple Bit Upset and automatic correction of Single Event Upset can be done with Single Error Correction and Double Error Detection code. These soft-error detection/recovery mechanisms cause cost/performance degradation. In this paper, probability of serious calculation failures occurred by SEU in an MIPS R3000 compatible processor core is evaluated. We investigate the probability using Register Transfer Level simulation. The result shows that impacts of SEU to calculation result differ much, when SEU happens in a Program Counter, an Instruction Register or register files. Soft error detection/recovery mechanism of an embedded processor core can be selected automatically when permitted soft error rate of an application program is given as a specification1.

W-CDMA Channel Codec by Configurable Processors

Abstract On development of mobile communication terminals, a trade-off among performance, development period, and implementation flexibility is one of the most important issues. In this paper, an efficient architecture of channel codec is explored, dedicatedly for W-CDMA mobile communication standard. A pair of configurable processors are employed in our implementation, which are assigned to Turbo decoding and remaining processes. A set of specific instructions are introduced to both of the processors so as to enhance the execution of computationally intensive functions, which successfully reduce the execution cycles by 98% and 60%, respectively. As a result, real-time processing can be achieved in short development period, demonstrating that our implementation is feasible solution against the trade-off.