Masanori Maruyama

An all-ASIC implementation of a low bit-rate video codec

After many years of intensive deliberation, an international low-bit-rate video coding standard, known as CCITT (International Telegraph and Telephone Consultative Committee) Recommendation H.261, has been completed. The H.261 covers a wide range of bit rates at p*64 kbs, where p=1, 2, . . ., 30. A great deal of real-time signal processing power is required to compress an NTSC or other similar video signals to these rates for transport and to reconstruct the original signal back for display. In order to demonstrate the video quality of the newly established standard and the feasibility of a cost-effective VLSI solution, a real-time video codec based on H.261 has been constructed using ASICs (application specific integrated circuits). A single-board research prototype consisting of 11 ASICs with an aggregate signal processing power of approximately two billion operations per second is presented. >

Variable-bit-rate HDTV codec with ATM-cell-loss compensation

A variable-bit-rate coding algorithm based on motion-adaptive discrete cosine transform (DCT) is investigated for asynchronous transfer mode (ATM) environments in broadband integrated-services digital networks (B-ISDN). The algorithm effectively reduces the bit rate, in particular, for HDTV-picture sources with little motion. Adaptive two-layered coding, an ATM cell matrix for error correction, and a block interleave for error concealment are proposed to keep picture quality high by compensating for ATM cell loss. A feedforward control scheme for variable-length coding (VLC), a multimode quantization that restricts peak bit rate and average bit rate, is also proposed for traffic control. Experimental hardware is shown to reduce the coding bit rate for pictures of HDTV conference applications to peak bit rate of 65-Mb/s and an average bit rate of 10-20-Mb/s in ATM environments. >

VLSI architecture and implementation of a multifunction, forward/inverse discrete cosine transform processor

The Discrete Cosine Transform (DCT) is considered to be the most effective transfonn coding technique for image and video compression. In this paper a new implementation of an experimental prototype multi-function DCT/IDCT (Inverse DCT) chip is reported. The chip is based on a distributed arithmetic architecture. The main features of the chip include: 1) The DCT and the IDCT are integrated in the same chip 2) the chip achieves high accuracy exceeding the stringent requirements of a proposed CCITF standard 3) it achieves a high operating speed of 27 MHz and is thus applicable to a wide-range of real-time image and video applications 4) the internal clock frequency is the same as the pixel rate and 5) with an on-chip zigzag scan converter and an adder/subtractor it is multifunctional and useful in a DPCM configuration. The chip is implemented with standard cells and contains about 156k transistors.

A flexible motion-vector estimation chip for real-time video codecs

The implementation of a versatile full-search block-matching motion estimation chip is described. This chip calculates a motion vector for a block, with a block size of 8*8, 16*16, or 32*32, and outputs the minimum block difference and the block difference of no motion. This chip is one of the most computationally intensive building modules in a video codec. A novel data flow design is reviewed, which allows sequential inputs and performs parallel processing with 100% efficiency. Implementation of this chip is targeted at high performance for real-time video compression. An optimization of the processing elements was performed using pipeline architecture to reduce the cycle time. Each comparison performed in the comparator module was distributed into two cycles to avoid speed bottleneck. Testing circuitry was included to reduce the huge testing patterns. The implementation was carried out by using 1 mu m CMOS technology. Simulation showed that 30 MHz operation can be achieved.<<ETX>>

Electrostatic focusing and electrostatic deflection systems with reduced aperture aberrations

Electrostatic focusing and electrostatic deflection (SS) electron beam systems have been investigated to increase the resolution of SS camera tubes. SS camera tubes have pattern electrodes formed on their inner walls. The pattern electrodes comprise deflection electrodes and a cylindrical electrode. The deflection electrodes form a band around the inner wall at one end of the tube. Four leads project longitudinally from this band, dividing the cylindrical electrode into four parts. An octopole lens is created around the leads of the deflection electrodes. To increase tube resolution, the electron optical characteristics were evaluated, taking into account the effects of the octopole lens. It was revealed that, due to the octopole lens, the aberration spot is not isotropic and its diameter is about three times that produced by a cylindrical lens. New pattern electrodes with zig‐zag shaped leads were devised. It was found that the aberration spot became almost round and its diameter was reduced to the value...

VLSI implementation of a buffer, universal quantizer, and frame-rate-control processor

The CCITT Recommendation H.261 describes the video coding and decoding method for the moving picture component of audiovisual services at the rates of p X 64 kbit/s, where p is in the range 1 to 30. Accordingly, several chip sets realizing these methods have been announced. In this paper, a new architecture and implementation of an adaptive coding controller chip is reported. The main feature of the chip include: (a) adaptive weighted image quality control capability, (b) high-speed operation, and (c) external control capability for coding control. The chip is implemented with CMOS standard cells and contains approximately 38,000 gates.