Masanori Shirahama

An 8 ns random cycle embedded RAM macro with dual-port interleaved DRAM architecture (D/sup 2/ RAM)

Recent multimedia applications and personal computers require enhanced memory systems. 3D-graphics and networking require faster random cycle and lower latency megabit-scale RAMs. However, the random cycle time of conventional DRAM is too slow and embedded SRAM area is too large to integrate high-density RAM on a chip. The fast random cycle low-latency embedded RAM macro reported here uses a dual-port interleaved DRAM architecture (D/sup 2/RAM). D/sup 2/RAM reduces random cycle time from 50 ns (20 MHz) of conventional DRAM to 8 ns (125 MHz) on a test chip with a 0.25 /spl mu/m embedded DRAM process. Key technologies are (1) interleaved open bitline operation with dual-port memory cell architecture, (2) two-stage pipelined circuit operation and (3) write before sensing (WBS).

A PND (PMOS-NMOS-Depletion MOS) Type Single Poly Gate Non-Volatile Memory Cell Design with a Differential Cell Architecture in a Pure CMOS Logic Process for a System LSI

A novel PND (PMOS-NMOS-Depletion MOS) technology for a single poly gate non-volatile memory cell design has been reported for the first time. This technology features memory cell design with a differential cell architecture which enables to provide the higher performance for the key specifications such as programming time, erasing time, and endurance characteristics. This memory cell consists of 3-Transistors, PMOS, NMOS, and Depletion MOS transistors (hereafter PND). The DMOS in this cell is used for the tunneling device in the erasing operation, while the NMOS and the PMOS are used for the tunneling device and the coupling capacitor in the programming operation, respectively. The proposed PND design can allow lower applied voltage of the erase-gate (EG) and control-gate (CG) in the erasing and the programming operations so that the endurance characteristics can be improved because the DMOS suppresses the potential of floating-gate (FG) and hence the effective potential difference between the EG and the FG can be increased in the erasing operation. Based on the measured data, it can be expected that the erasing speed of the PND cell can be 125-fold faster than that of our previously reported work (PN type). Therefore, high performance and high reliability CMOS non-volatile memory without any additional process can be realized using this proposed PND technology.

A 400MHz random-cycle dual-port interleaved DRAM with striped-trench capacitor

We present a 400MHz random-cycle dual-port interleaved 1.5V DRAM macro with fully sense-signal-loss compensating technologies based on noise-element breakdowns, a striped trench capacitor cell and write-before-sensing by a decoded write-bus circuit technique. The IC is implemented in a 0.15 /spl mu/m CMOS logic process.

A 400-MHz random-cycle dual-port interleaved DRAM (D/sup 2/RAM) with standard CMOS Process

This paper describes a standard CMOS process based on embedded DRAM macro with dual-port interleaved DRAM architecture (D/sup 2/RAM), which is suitable for the leading edge CMOS LSIs with both high-speed and large-scale memories on a chip. This macro exploits three key technologies: fully sense-signal-loss compensating technology based on the whole detailed noise element breakdowns, the novel striped trench capacitor (STC) cell, and the write-before-sensing (WBS) circuit by decoded write-bus. A 400-MHz random cycle access has been verified for D/sup 2/RAM fabricated by a 0.15-/spl mu/m standard CMOS process.