Masanori Tsukuda

Critical IGBT Design Regarding EMI and Switching Losses

Critical N-base layer design in IGBT is discussed regarding electro-magnetic interference (EMI) and switching losses during turn-off. The newly proposed criteria for oscillation and avalanche induced loss were given by a simple equation model and the validity of the model has been confirmed with experimental results. This paper shows an efficient design method of N-base for EMI-free IGBT with considering the turn-off loss. In addition, EMI reduction structure with partly buried N layer in N-base was proposed for break through the design limit of N-base.

High Power Density Converter using SiC-SBD

This paper reports on the possibility of a high output power density converter by demonstrating a small volume DC-DC down converter using a 600 V superjunction MOSFET (SJ-MOSFET) and silicon carbide Schottky barrier diode (SiC-SBD). The output power density of the demonstrated DC-DC down converter was 50 W/cc, which is the future target of high power density converters.

New anode design concept of 600V thin wafer PT-IGBT with very low dose p-buffer and transparent p-emitter

We propose 600V new thin wafer PT (Punch Through) IGBT having a new concept of anode design. This proposed PT-IGBT has a very low dose p-type layer, called p-buffer, between a transparent p-emitter (anode) and an n-buffer layer. This provides a practical design for easy fabrication without deteriorating the good feature of the thin wafer PT-IGBTs. The n-buffer dose and the p-emitter dose can be precisely controlled by the doses of the two ion implantations. This is great merit in precise control of the p-emitter injection efficiency. An oscillation in the turn-off waveforms also disappears for the proposed PT-IGBT with p-buffer layer, because a smooth turn-off is achieved by a small tail current. The total power loss is not affected by the small tail loss.

Dynamic punch-through design of high-voltage diode for suppression of waveform oscillation and switching loss

The authors analyzed the surge voltage causing the oscillation in detail and found that the peak electric field at punch-through EP is proportional to the maximum surge voltage. The maximum surge voltage can be decreased by shifting the punch-through position WP toward the cathode side because the WP shift leads EP lowering. This dynamic punch-through design is applicable for whole operating condition. Based on the above discussions, a PIN-diode with a novel structure was invented that achieves the ideal carrier profile for shifting the WP closer to the cathode side with high electron injection during low-current operation. The simulation results show the maximum surge voltage causing oscillation was suppressed to about 50% lower and the switching loss of the diode also decreased to about 60% lower in the same time compared with the conventional structure.

A 600V Deep-Implanted Gate Vertical JFET

A 4H-SiC 600V class Deep-Implanted gate Vertical JFET (DI-VJFET) is reported. To achieve lower on-resistance and higher blocking-voltage, the design of channel region plays an essential role. Therefore, the channel dimensions were optimized with the ISE device simulator and calculated results were compared with experimental results. Moreover, the actual channel dimensions of fabricated samples were analyzed by SSRM (Scanning Spread Resistance Microscopy) measurements. The potential distributions in on/off-state were analyzed by SPoM (Scanning Potential Microscopy) measurements. The active areas of 2.2x10 -3 , 1.6x10 -2 [cm 2 ] (small chip), and 5.3x10 -2 [cm 2 ] (large chip) were fabricated, in this study. The small chips were evaluated to ascertain the dependence of the electric characteristics on the design parameters. The blocking-voltages were varied up to 1100V, and the on-resistances were varied down to 7.8mΩcm 2 depending on the fabricated channel opening. The DI-VJFET in this work has almost the same electric characteristics as Si Cool-MOSFET. The large chips exhibited specific on-resistance of 16mΩcm 2 , drain current of 5A, and blocking-voltage of 900V. The turn-off speed of the large chip was measured with resistive load circuit. The turn-off time was 200ns for external resistance of 60Ω.