Tomoko Matsudai

Multi-channel SOI lateral IGBTs with large SOA

We report, for the first time, the development of 5 ampere multi-channel lateral IGBTs on SOI. The new LIGBTs are characterized by a plural number of parallel stripe poly-silicon gates and resultant plural number of channels, which enhances electron injection and attains a large current capability. The developed LIGBTs conduct current density over 120 A/cm/sup 2/ at the drain voltage of 3 V and simultaneously achieve a fall-time below 300 ns. The LIGBTs have excellent current capability and short circuit withstanding capability of DC 300 V with 500 A/cm/sup 2/ of drain current even at 200/spl deg/C.

Advanced 60 /spl mu/m thin 600 V punch-through IGBT concept for extremely low forward voltage and low turn-off loss

A vertical trench gate 600 V PT (Punch Through) IGBT structure with a new concept of thin substrate wafer with a low dose n-buffer and a transparent p-emitter is proposed to realize an excellent trade-off relation between the device on-state voltage and the switching speed. In this paper, we have fabricated and evaluated 600 V/150 A rated thin wafer PT IGBT in a 60 /spl mu/m thin silicon substrate. It was experimentally confirmed that 60 /spl mu/m PT IGBTs with a transparent p-emitter have an excellent trade-off relation for room temperature and 125/spl deg/C. Especially the fabricated 60 /spl mu/m thin 600 V PT IGBTs have realized an on-state voltage as low as 1.23 V at 150 A/cm/sup 2/ current density with an extremely short fall-time of 60 ns for 25/spl deg/C.

New anode design concept of 600V thin wafer PT-IGBT with very low dose p-buffer and transparent p-emitter

We propose 600V new thin wafer PT (Punch Through) IGBT having a new concept of anode design. This proposed PT-IGBT has a very low dose p-type layer, called p-buffer, between a transparent p-emitter (anode) and an n-buffer layer. This provides a practical design for easy fabrication without deteriorating the good feature of the thin wafer PT-IGBTs. The n-buffer dose and the p-emitter dose can be precisely controlled by the doses of the two ion implantations. This is great merit in precise control of the p-emitter injection efficiency. An oscillation in the turn-off waveforms also disappears for the proposed PT-IGBT with p-buffer layer, because a smooth turn-off is achieved by a small tail current. The total power loss is not affected by the small tail loss.

200/spl deg/C high-temperature and high-speed operation of 440 V lateral IGBTs on 1.5 /spl mu/m thick SOI

This paper experimentally verifies that high-voltage lateral IGBTs fabricated on SOI of less than 5 /spl mu/m exhibit high switching speed without the need for any special device design. This paper also verifies, for the first time, that thin SOI is a promising candidate for 200/spl deg/C high-temperature operation, because switching speed does not deteriorate at high temperature.<<ETX>>

A trench-gate injection enhanced lateral IEGT on SOI

This paper reports, for the first time, that lateral IGBTs with an injection enhanced multiple trench gate structure (LIEGT) on SOI successfully achieved both a low forward voltage drop and a high switching speed. The current density of LIEGTs with two trench gates is more than twice as large as that of conventional lateral IGBTs on a 10 /spl mu/m SOI. Closely spaced deep trench gates result in carrier storage under the trench gates and enhance lateral carrier flow. Although the switching speed of 10 /spl mu/m SOI LIEGTs is as fast as that of LIGBTs, its switching loss can be reduced. Thus, the electrical characteristics of lateral trench gate IEGTs on SOI are quite good.

Simulation of a 700 V high-voltage device structure on a thin SOI - substrate bias effect on SOI devices

This paper shows for the first time that a 700 V breakdown voltage is easily realized in a uniformly doped thin SO1 structure without using a complicated impurity profile when a SIPOS resistive field plate is utilized. The electric field inside the thin SO1 is uniformly distributed by the influence of the SIPOS layer when they are closely located to each other. This paper also shows the effects of substrate bias on the SO1 device characteristics. Relatively thick SO1 devices become free from substrate bias effects,since the negative substrate bias is shielded by a created p-channel on the bottom oxide.

1200V SC(Schottky controlled injection)-diode, an advanced fast recovery concept with high carrier lifetime

In this paper, a 1200V novel PiN-diode concept realizing low forward voltage drop (VF), low reverse recovery loss and low leakage current at high temperature over 175°C has been proposed. To realize these above-mentioned characteristics, this concept of 1200V diode design adopts a combination of flat and linear distribution of carrier concentration from anode side to cathode side and reducing injection efficiency at both sides at forward bias condition. This carrier profile can also realize reduction of voltage ringing effectively at reverse condition. Furthermore, we have successfully obtained high reverse recovery ruggedness combining a new edge termination design with Schottky contact.

Ultra high switching speed 600 V thin wafer PT-IGBT based on new turn-off mechanism

A new turn-off mechanism for 600 V thin wafer PT-IGBTs (punch-through IGBTs) has been found and ultra high speed switching has been demonstrated, for the first time, in this paper. The new turn off process makes it possible to operate IGBTs in a quasi-MOSFET mode in the turn-off transient, realizing ultra high speed switching. Most of the stored carriers in the n-drift region can be automatically removed, without any additional means, in the storage time period, before the voltage recovery process. This results in extremely low dissipated power loss and substantially eliminates tail current. Furthermore, this paper described the results of numerical investigation and measured characteristics of the sustaining mode operation. When the p-emitter efficiency of thin wafer PT-IGBTs was decreased, the sustaining voltage was larger than the static breakdown voltage and most of the current was supplied by impact ionization due to poor p-n-p transistor action. Thin wafer PT-IGBTs with reduced p-emitter efficiency behave like quasi-MOSFETs.

Evaluation of 0.3.MU.m Poly-Silicon CMOS Circuits for Intelligent Power IC Application.

In this paper, we report on the fine device performance of a 0.3 µm gate length polysilicon complementary metal-oxide-semiconductor (CMOS). The breakdown voltage of 0.3 µm n-channel metal-oxide-semiconductor field effect transistor (NMOSFET) devices exceeds 6 V, which is higher than that of NMOSFET devices on separation by implanted oxygen (SIMOX) wafer. The drain current of a 10 µm channel width device is 540 µA, which is one-fifth of that of NMOSFET on SIMOX. The leakage current is less than 10-11 A/µm, when the gate voltage is below 0 V. The S-factor is 125 mV/dec, and the threshold voltage is 0.4 V. Therefore the ON/OFF current ratio is greater than 107. A delay time of 1 ns is achieved in polysilicon NAND rings. Hence, it is ascertained that the polysilicon CMOS is applicable for the fabrication of control and protection circuits on power devices.

Thin SOI IGBT leakage current and a new device structure for high temperature operation

This paper describes and compares the temperature dependence of leakage current and on-state resistance of MOSFETs (diodes) and LIGBTs on thin SOI. The leakage current decreases effectively as the SOI layer thickness decreases. The forward voltage-drop of IGBTs on thin SOI is not significantly deteriorated at a high temperature, such as 200/spl deg/C. On the other hand, switching speed improves as the SOI layer thickness decreases. Thus, a thin SOI device is a good candidate for high temperature operation.