Masao Mizukami

32*32 shared buffer type ATM switch VLSIs for B-ISDNs

A set of 0.8 mu m CMOS VLSIs developed for shared buffer switches in asynchronous transfer mode (ATM) switching systems is described. A 32*32 unit switch consists of eight buffer memory VLSIs, two memory control VLSIs, and two commercially available first in first out (FIFO) memory LSIs. Using the VLSIs, the switch can be mounted on a printed board. To provide excellent traffic characteristics not only under random traffic conditions but also under burst traffic conditions, this switch has a 2-Mb shared buffer memory, the largest reported to date. which can save 4096 cells among 32 output ports. This switch has a priority control function to meet the different cell loss rate requirements and switching delay requirements of different service classes. A multicast function and a 600 Mb/s link switch architecture, which are suitable for ATM network systems connecting various media, and an expansion method using the 32*32 switching board to achieve large-scale switching systems such as 256*256 or 1024*1024 switches are discussed. >

32*32 shared buffer type ATM switch VLSIs for B-ISDN

A set of 0.8 mu m CMOS VLSIs developed for shared buffer switches in asynchronous transfer mode (ATM) switching systems is described. A unit switch, whose size is 32*32, consists of 8 buffer memory LSIs (BFM-LSIs), 2 memory control LSIs (CTRL-LSIs) and 2 commercially available first in, first out (FIFO) memory LSIs. Using these VLSIs, the 32*32 switch can be mounted on a printed board. This switch is a shared buffer switch. It achieves buffer memory utilization improvement through the use of buffer sharing among all output ports of the switch and has a large 2-Mbit shared buffer which can save 4096 cells. As a result, this switch can satisfy the cell loss rate requirements, not only under random traffic conditions but also under burst traffic conditions. The switch has a priority control function to meet the requirements for various media. It is useful for multimedia ATM networks.<<ETX>>

A high performance switch for OC-12 SONET self-healing ring networks

The progress of ITU-T and ANSI standards on SDH/SONET is accelerating the evolution of transmission systems all over the world. The advanced operation administration and maintenance (OAM) functions it provides makes it possible to create a self healing ring network which protects against failure. This self-healing ring consists of add/drop multiplexers (ADMs). The switch in the ADM plays an important role in achieving self-healing operation. In this paper, self-healing ring architecture and operations are analyzed in order to determine the requirements for the ADM switch. On the basis of this result, new space division switching methods, which significantly reduce the amount of hardware needed, are proposed. A parallel processing architecture which makes it possible to develop a low-cost large-scale switch is also devised. Finally, a developed switch LSI chip is presented. Combining two identical chips with the proposed parallel processing architecture, a 32/spl times/32 STS-3 switch (5 Gb/s throughput) with an STS-1 time slot interchange (TSI) function is realized.