Takahiko Kozaki

Shared buffer memory switch for an ATM exchange

An asynchronous transfer mode (ATM) switch architecture called a shared buffer memory switch whose output cell buffers are shared among all the output ports of the switch is proposed. Experimental measurements and a discussion about the traffic characteristics of the switch architecture are carried out to determine how much buffer memory will be reduced through buffer sharing under various traffic conditions and to roughly estimate how many buffers are needed for the switch to meet certain requirements. The resultant estimate shows that buffer sharing reduces the necessary buffer memory to less than 1/5 of what would otherwise be required, and the required buffer size is about 128 cells/output for a 32*32 switch when considering bursty traffic conditions. LSI implementation is also discussed to show that a 32*32 switch can be composed of about 12 chips mounted on one printed board. >

A shared buffer memory switch for an ATM exchange

The authors propose a shared buffer memory switch in which output buffer memories are shared by all the switch output ports and are alloted to one particular output port as the occasion demands. This switch architecture can further improve the hardware-utilization efficiency of the memory switch by increasing the buffer memory usage rate. A discussion on switch traffic characteristics is provided and indicates that buffer sharing reduced the required memory size to less than 0.14 of that otherwise required for adequate switch size and estimates roughly the buffer size required for the switch. The large scale integration (LSI) count, for example, is about 15 chips for the main part of a 32*32 switch (150 Mb/s for each port) which can be mounted on one printed board. The switch is partitioned into a buffer memory LSI and a control LSI to make them flexible to change in ATM switch specifications.<<ETX>>

32*32 shared buffer type ATM switch VLSIs for B-ISDNs

A set of 0.8 mu m CMOS VLSIs developed for shared buffer switches in asynchronous transfer mode (ATM) switching systems is described. A 32*32 unit switch consists of eight buffer memory VLSIs, two memory control VLSIs, and two commercially available first in first out (FIFO) memory LSIs. Using the VLSIs, the switch can be mounted on a printed board. To provide excellent traffic characteristics not only under random traffic conditions but also under burst traffic conditions, this switch has a 2-Mb shared buffer memory, the largest reported to date. which can save 4096 cells among 32 output ports. This switch has a priority control function to meet the different cell loss rate requirements and switching delay requirements of different service classes. A multicast function and a 600 Mb/s link switch architecture, which are suitable for ATM network systems connecting various media, and an expansion method using the 32*32 switching board to achieve large-scale switching systems such as 256*256 or 1024*1024 switches are discussed. >

Traffic characteristics evaluation of a shared buffer ATM switch

The performance of a shared buffer memory ATM (asynchronous transfer mode) switch that was investigated by hardware emulation is discussed. Cell loss ratio under balanced and unbalanced traffic conditions is considered. It is found that the buffer size of an 8*8 shared buffer switch is reduced by a factor of five compared to that of the separate buffer switch, under both random and bursty traffic conditions when the offered load is uniformly distributed across all output ports. However, when unbalanced traffic is offered to the switch, the advantage of buffer sharing is diminished and the performance degrades. This is prevented by employing a simple control strategy which consists of limiting the number of cells in the queue destined for a particular output port to a fraction of the total buffer size. It is shown that the optimal queue length limitation is about one half of the total buffer capacity of the switch.<<ETX>>

32*32 shared buffer type ATM switch VLSIs for B-ISDN

A set of 0.8 mu m CMOS VLSIs developed for shared buffer switches in asynchronous transfer mode (ATM) switching systems is described. A unit switch, whose size is 32*32, consists of 8 buffer memory LSIs (BFM-LSIs), 2 memory control LSIs (CTRL-LSIs) and 2 commercially available first in, first out (FIFO) memory LSIs. Using these VLSIs, the 32*32 switch can be mounted on a printed board. This switch is a shared buffer switch. It achieves buffer memory utilization improvement through the use of buffer sharing among all output ports of the switch and has a large 2-Mbit shared buffer which can save 4096 cells. As a result, this switch can satisfy the cell loss rate requirements, not only under random traffic conditions but also under burst traffic conditions. The switch has a priority control function to meet the requirements for various media. It is useful for multimedia ATM networks.<<ETX>>

Datapath architecture and technology for large scale ATM switching systems

Datapath architecture and technologies for large scale switching systems are studied. Two main key-factors, the complexity of the functional blocks such as the switch fabric, and the interconnection between the functional blocks should be considered. This paper mainly focuses on the interconnection, which is the most important issue to be resolved before achieving a practical multi-hundreds-Gbps switching system. The complexity of the switch fabric would not be the constraints considering the progress of very large scale integrated circuit (VLSI) technology, which allows more than one-mega gates on a chip. Many aspects of interconnection technologies have been investigated including switch fabric functional allocation to functional blocks, datapath width expansion between VLSI chips or shelves, and high-speed transmission utilizing CMOS and optical technologies. This paper also shows a single card ATM unit switch with a throughput of 20-Gbps as an example of the feasibility of these technologies.

PVC reservation on shared buffer type ATM switch for data communication

This paper describes an ATM switch with a PVC (permanent virtual connection) reservation function, which reserves a PVC identifier when each cells stream arrives at the switch unless the sum of the peak bandwidths of the cell streams exceeds the output link throughput of the switch. Only reserved PVC cell streams can pass through the switch completely without interference from unreserved streams. We have already developed one-board ATM switch forming 128 queues on the 4,000-cell shared buffer for bandwidth control. It is feasible to achieve a PVC reservation by allotting one PVC cell stream to one queue at the switch forming multiple queues for each output port.<<ETX>>

Large scale ATM switch architecture for Tbit/s systems

This paper discusses a large-scale ATM switch architecture toward a T(tera) bit/s system. A single-stage 40-Gbit/s ATM switch was developed using a parallel processing architecture incorporating current 0.35 /spl mu/m-CMOS device technology and conventional printed circuit boards (300mm/spl times/300mm approx.). This architecture is applicable to a 160-Gbit/s switch using the latest 0.25 /spl mu/m-CMOS device technology. Moreover, a scalable solution for different smaller capacity switches using the same switch elements is introduced. This paper also introduces an innovative method for switch capacity extension. By employing the multipath parallel distribution approach at the cell level with cell sequence integrity guaranteed, this method enables an existing switch to be efficiently expanded.

A large scale ATM switching system architecture for multimedia communications

1 . Introduction Multimedia communications are having a great impact on switching system architecture . The Asynchronous Transfer Mode (ATM) is the predominant technique used to obtain a B-ISDN with a universal interface . Next-generation switching using this technique must have a flexible architecture to handl e the heterogeneous traffic and sophisticated services multimedia communications will provide . To adapt to the increase of B-ISDN subscribers, we propose a hyper-distributed switching system architecture composed of a non-intelligent module and independent modules with call processing functions . To multiplex burst traffic , ATM shared buffer memory switches are used as the unit switches in both modules .