Masaru Kokubo

A UWB-IR Transmitter With Digitally Controlled Pulse Generator

A novel transmitter for ultra-wideband (UWB) impulse radio has been developed. The proposed architecture enables low-power operation, simple design, and accurate pulse-shape generation. The phase and amplitude of the pulse are controlled separately and digitally to generate a desired pulse shape. This digital control method also contributes to the low-power transmission and eliminates the need for a filter. The transmitter is fabricated using a 0.18-mum CMOS process. The core chip size is only 0.40 mm2. From experimental measurements, it was found that the generated signal satisfied the FCC spectrum mask, and the average power dissipation was only 29.7 mW at A 2.2-V supply voltage. Therefore, the developed UWB transmitter generates accurate pulses with low power consumption and simple design architecture

Spread-spectrum clock generator for serial ATA using fractional PLL controlled by /spl Delta//spl Sigma/ modulator with level shifter

Implemented in a 0.15/spl mu/m CMOS process, the spread-spectrum clock generator uses the fractional PLL controlled by a /spl Delta//spl Sigma/ modulator An adaptive level shifter is adopted for expanding the input range of the /spl Delta//spl Sigma/ modulator. The 1.5GHz prototype achieves the peak spurious reduction level of 20.3dB and the random jitter of 8.1 ps in a 250-cycle averaging period.

A novel UWB impulse-radio transmitter with all-digitally-controlled pulse generator

A novel transmitter for ultra-wideband (UWB) impulse radio was developed. The proposed architecture realizes low power, low complexity, and generation of a highly accurate pulse. The phase and amplitude of a pulse are controlled separately and digitally to generate a highly accurate pulse. This control method also contributes to the transmitters low power and eliminates the need for a filter. The transmitter was fabricated by a 0.18-/spl mu/m bulk CMOS process. The core chip size is only 0.40 mm/sup 2/. Measurement of this transmitter found that the FCC spectrum mask is satisfied and average power dissipation is 29.7 mW under a supply voltage of 2.2 V. These results show that the developed UWB transmitter can generate an accurate pulse with low power and low complexity.

A fast-frequency-switching PLL synthesizer LSI with a numerical phase comparator

A synthesizer fabricated in a single chip requires 3 improvements: (1) new numerical phase comparator using a digital differential phase comparator (DDPC) that avoids frequency offset, (2) digital loop filter (DLF) that has notch frequency characteristics at the frequency step to suppress the DDPC noise, (3) interpolation using a /spl Sigma//spl Delta/ modulator must be used to implement a 20 b resolution digital-to-analog converter (DAC). The architecture of a PLL frequency synthesizer with numerical phase comparator, which satisfies these requirements, is described. The PLL frequency synthesizer, consists of the DDPC, DLF, /spl Sigma//spl Delta/ modulator, DAC, LPF (low pass filter), and VCO. The DDPC calculates the phase difference between the output of the VCO and the reference clock. The DLF filters out the DDPC noise. The output of the DLF is converted into an analog signal by the DAC and used to control the VCO. The PLL synthesizer LSI is in 0.6 /spl mu/m BiCMOS and the chip area is 5.69/spl times/5.51 mm/sup 2/. Total current is 20 mA, when the supply voltage is 4.5 V for the analog circuit and 3.3 V for the digital circuit. Switching time is <0.7 ms at a 16 MHz hopping frequency. No spurious components are observed and spurious level is <-75 dBc at a 25 kHz offset frequency due to the notch filter in the DLF.

Rapid signal acquisition for low-rate carrier-based ultra-wideband impulse radio

In this paper, a rapid signal-acquisition method is proposed for carrier-based ultra-wideband impulse-radio systems in low-data-rate applications such as sensor networks. For low-data-rate ultra-wideband impulse radio systems, highly precise synchronization must be established over relatively long periods. In the proposed method, signal-acquisition times are reduced by assigning different blocks responsibility for synchronization with the pulse and with the spreading code. Furthermore, dividing up the symbols to produce a smaller unit for integration enables signal acquisition even when there is a realistic difference between the transmitter and receiver-local frequencies. Results of simulation indicate that, for a given Eb/N0, the proposed method reduces acquisition times from those required by the conventional method.

A 2.4 GHz RF transceiver with digital channel-selection filter for Bluetooth

An RF transceiver chip for Bluetooth that uses a digital channel-selection filter is 3.3/spl times/3.4 mm/sup 2/ in size. It is realized by decrease of the analog area using the digital channel selection filter. The test chip uses 0.35 /spl mu/m BiCMOS.

Spread-Spectrum Clock Generator for Serial ATA with Multi-Bit ΣΔ Modulator-Controlled Fractional PLL

We have developed a spread-spectrum Phase-Locked Loop (PLL) for serial Advanced Technology Attachment (ATA) applications. We investigated the relation between the output jitter of PLLs in serial ATA applications and ΣΔ modulators in PLLs. On the basis of this study, we developed a spread-spectrum PLL for serial ATA applications and achieved a combination of small jitter and large electromagnetic interference (EMI) peak power reduction. This was achieved using two key components: multi-bit SA-controlled PLL and voltage-controlled oscillation with cross-coupled load delay cells. Using a 0.15-μm complementary metal-oxide semiconductor process, we fabricated a complete serial ATA transceiver featuring a spread-spectrum clock generator (SSCG). We achieved a spread-spectrum PLL with 10-dB EMI reduction and 8.1 ps random jitter for use in serial ATA applications. All other measured results for SSCG performance were very good and showed that the spread-spectrum generator more than satisfies serial ATA specifications.

Intermittent Wireless Communication System for Low-Power Sensor Networks

An intermittent wireless communication system has been developed for low-power sensor networks that improves sensor network efficiency by promoting cooperative optimization among the hardware architecture, communication protocol, and multiple access scheme. The intermittent communication protocol together with hardware for intermittent function contributed to reduce power consumption and extended sensor-node battery lifetime. A multiple access scheme based on the R-ALOHA protocol is used for the wireless link; it works efficiently with the protocol and hardware. Due to its inter-layer optimization, the system has low power consumption regardless of the traffic load and is thus flexible enough to support a wide range of sensor network applications.

0.7-GHz-Bandwidth DS-UWB-IR System for Low-Power Wireless Communications

A direct-sequence ultra-wideband impulse radio (DSUWB-IR) system is developed for low-power wireless applications such as wireless sensor networks. This system adopts impulse radio characterized by a low duty cycle, and a direct-sequence 0.7-GHz bandwidth, which enables low-power operation and extremely precise positioning. Simulation results reveal that the system achieves a 250-kbps data rate for 30-mdistance wireless communications using realistic specifications. We also conduct an experiment that confirms the feasibility of our system.

A dual-band transceiver for GSM and DCS1800 applications

In this paper we present a dual-band transceiver IC for small, low cost handsets for GSM and DCS1800 applications. The IC fabricated in a 0.6-µm BiCMOS process includes a transmitter using the offset phase locked loop (OPLL) technique and a dual IF receiver. The evaluation results of the system containing the IC show the phase error of 3.0°rms (GSM) and 2.1°rms (DCS1800) for the transmitter, and the reference sensitivity of -106.2 dBm (GSM) and -105.9 dBm (DCS1800) for the receiver.