Masashi Shimanouchi

An approach to consistent jitter modeling for various jitter aspects and measurement methods

Timing jitter, period jitter, long term jitter, jitter spectrum, SSB phase noise, etc. are terms that have been used to describe various aspects of jitter phenomena. While several jitter measurement techniques have been proposed with associated jitter models and modeling techniques, the relationship among various jitter aspects, and therefore, the relationship among various jitter measurement techniques is not very obvious. This paper analytically clarifies their relationship, and reviews several jitter measurement techniques based on the results of our analytical studies.

New paradigm for signal paths in ATE pin electronics are needed for serialcom device testing

Signal paths in ATE pin electronics need a fresh examination in order to address the challenges of serial data communication (serialcom) device testing. The effects of limited frequency bandwidth of the DUT signal path can introduce nonnegligible amounts of data-dependent jitter in the jitter testing. This effect has not been previously discussed with respect to ATE. The frequency bandwidth effects become even more critical at the speeds expected in the near future. This paper proposes new signal paths in ATE, studies the basics of the tools used for frequency bandwidth investigation and reviews some fundamental frequency bandwidth effects in ATE.

Tester architecture for the source synchronous bus

A majority of digital logic devices receives stimulus from an external system clock and sends information out on bus pins which are synchronized to the system clock. During functional testing of such devices, ATE architectures supply the clock and input data signals. The output signals generated by these devices are synchronous to the tester and are sampled accurately by the test equipments strobe circuits. With the emergence of wide data busses in memories and high speed communication protocols implemented to transfer data between the CPU and peripherals, it has become necessary to forward a clock along with a group of bus pins to maintain skew across the high speed bus pins to an acceptable value for system design. This has resulted in a class of devices which have source synchronous busses where output signals are sent out relative to their strobe (output clock) signals. This work describes the challenges associated with testing this class of devices with the classical automatic test equipment (ATE) architecture and presents a unique hardware solution implemented on a contemporary tester architecture to meet the test challenge. This work also compares this implementation with other solutions available in the ATE domain.

New modeling methods for bounded Gaussian jitter (BGJ)/noise (BGN) and their applications in jitter/noise estimation/testing

We propose a new method for modeling and quantifying bounded Gaussian jitter (BGJ), as well as bounded Gaussian noise (BGN). The validity and accuracy of the method are illustrated and verified both in theory and experiments. We then demonstrate the applications of this new method for jitter and noise estimation and testing, especially for total jitter (TJ) and total noise (TN) at a targeting bit error rate (BER) level. We illustrate the accuracy improvements with this new method over the conventional methods that do not take BGJ or BGN into account.

Timing accuracy enhancement by a new calibration scheme for multi-Gbps ATE

The ever increasing data rate of high speed I/Os has required higher test timing accuracy. In order to keep improving ATEs edge placement accuracy, we have reviewed the traditional timing calibration methods in detail, and studied the timing error mechanism. Then we have developed a new calibration scheme to overcome the fundamental issues in some traditional calibration methods. Our main focus in This work is on the following three areas: data dependent jitter (timing error), pin-to-pin skew and calibration at DUT.

Theory, model, and applications of non-Gaussian probability density functions for random jitter/noise with non-white power spectral densities

In high speed data communications, timing jitter and voltage noise analyses often depend on mathematical models to predict long-term reliability of the system, typically merited by a low bit error ratio (BER). Many methods involve the extrapolation of random jitter (RJ) and random noise (RN) to very low BER, assuming that RJ is white Gaussian noise. In reality, RJ spectra are not always white. Thus, RJ statistical distributions can deviate from an ideal Gaussian, affecting the accuracy of extrapolations. This paper presents a theory and model for relating RJ distributions with colored spectra. We apply this model to various filtered RJ spectra, including the extreme case of Brownian (1/f2) noise, and show correlation between simulation and measurement.

Advancements in high-speed link modeling and simulation (An invited paper for CICC 2013)

As the high-speed I/O (HSIO) and serial link data rate keeps increasing, the requirements for accuracy and advanced capabilities of its modeling and simulation techniques get more stringent. Emerging requirements such as comprehending process, voltage, and temperature (PVT) variations at deep sub-micron process nodes or smaller, fully accounting for all the circuit blocks of the link, gap closing between modeling and measurements, have become critical and important, yet the conventional modeling and simulation methods cannot meet most or all of those requirements. In this paper, we will start with reviewing the status of techniques/methods used in recent HSIO simulation and modeling for signaling, integrated circuits (ICs), board circuits, such as behavioral statistical, SPICE and IBIS-AMI, outlining areas where they fall short, in comparison with those emerging requirements. We then will discuss the new methods and techniques that can meet and comprehend these emerging requirements and how they enhance and advance the accuracy and capability for the HSIO link modeling and simulation. We will give simulation and experimental results to demonstrate and quantify how to meet emerging requirements, as well as needed accuracy and capability advancements, with the new techniques.