Sergey Shumarayev

Interconnect enhancements for a high-speed PLD architecture

As programmable logic grows more viable for implementing full design systems, performance has become a primary issue for programmable logic device architectures. This paper presents the high-level design of Dali, a PLD architecture specifically aimed at performance-driven applications. We will present significant portions of the background research that contributed to our architectural decisions, an overview of the core routing architecture and benchmarking experiments used to evaluate the prototype device.

A signal integrity-based link performance simulation platform

This paper embodies a methodology used to create high-speed transceiver behavior models employed within a signal integrity-based link simulation platform. This tool includes routines for the optimization of transmitter pre-emphasis and equalization. This platform was created using MATLAB, qualified against Agilents ADS SI suite, and correlated with measurements. This paper also describes the practical uses of such a simulator developed at Altera to predict link performance over backplanes.

A 3.1mW phase-tunable quadrature-generation method for CEI 28G short-reach CDR in 28nm CMOS

Generating quadrature phases at low area and power overhead from a two-phase clock without frequency conversion is desirable for half-rate CDR architectures. This is useful for both embedded and forwarded clock systems, where quadrature generation by dividers, ring oscillators or coupled LC-VCOs is common. For example, [1] uses LC-VCOs followed by 2:1 dividers to generate the half-rate clocks for both TX and RX in a 28Gb/s transceiver. However, such an approach tends to be power- and area-inefficient for multi-lane implementations at data rates of 25Gb/s and beyond.

Arria™ 10 device architecture

This paper presents the architecture of Arria 10, a high-density FPGA family built on the TSMC 20SOC process. The design of the device includes an embedded dual-core 1.5 GHz ARM A9 subsystem with peripherals, more than 1M logic elements (LEs) and 1.7M user flip-flops, and 64Mb of embedded memory organized into configurable memory blocks. The Arria 10 family is also the first mainstream FPGA family to include hardened single-precision IEEE 754 floating point, with an aggregate throughput of 1.3 TFLOPs. Device I/O consists of 28G programmable transceivers with an enhanced PMA architecture hardened PCIe sub-blocks and hardened DDR external memory controllers. New methods for digitally-assisted analog calibration are used to address process variation. The fabric is optimized for an aggressive die-size reduction and power improvement over 28nm FPGAs and includes features such as time-borrowing FFs for micro-retiming, tri-stated long-lines for improved routability, programmable back-bias at LAB-cluster granularity and power-management features such as Smart-VID for balancing leakage and performance across the process distribution.

Emerging standards at ∼10 Gbps for wireline communications and associated integrated circuit design and validation

We first review the signaling and jitter requirements for emerging high-speed wireline communication standards at ∼10 Gbps, including CEI 11G, XLAUI/CAUI, XFI, and SFP+. We then present an FPGA transceiver architecture and subsystem/circuit blocks for clocking and timing generation, transmitter buffer, and receiver CDR and DFE, all designed and manufactured with 40-nm process node. Lastly, we present the signal/jitter transmitter output and receiver-tolerance measurement results at 10.3125 Gbps, with an ultra-low random jitter at ∼550 fs.

On-die instrumentation to solve challenges for 28nm, 28Gbps timing variability and stressing

Moving to the latest submicron node is required for digital scaling but causes many challenges for analog design. Additionally, scaling pushes the need for higher bandwidth. Data rates up to 28Gbps require effectively dealing with random variations and layout dependent effects. On-die instrumentation (ODI) is an effective means to alleviate many of the challenges, as well as characterize and margin performance. This paper covers two of the ODI techniques used in the design of a wide range 28nm, 28Gbps transceiver.

Receiver Offset Cancellation in 90-nm PLD Integrated SERDES

A wide-range transceiver was designed and fabricated in a 90-nm TSMC CMOS logic process. Each transceiver channel contains a transmitter and receiver with clock data recovery (CDR) circuit. The range of operation for this transceiver is from 622 Mbps to 6.5 Gbps. Voltage offsets in the receive path degrade the performance of the transceiver by putting a lower bound on the precision with which a data bit can be measured In addition to raising the minimum input voltage that can be correctly detected by the CDR, offsets in receive path cause duty cycle distortion, which, added with inter symbol interference (ISI), reduce the overall margin of data recovery directly worsening the bit error rate (BER). Presented in this paper is a methodology to cancel voltage offsets in the receive path with a soft intellectual property (IP) core programmed in the PLD.