Masataka Hoshino

High-Aspect-Ratio Copper Via Filling Used for Three-Dimensional Chip Stacking

Through-chip electrodes for three-dimensional packaging can offer short interconnection and reduced signal delay. Formation of suitable vias by electrodeposition into cavities presents a filling problem similar to that encountered in the damascene process. Because via dimensions for through-chip filling are larger and have a higher aspect ratio relative to features in damascene, process optimization requires modification of existing superconformal plating baths and plating parameters. In this study, copper filling of high-aspect-ratio through-chip vias was investigated and optimized with respect to plating bath composition and applied current wavetrain. Void-free vias 70 mu m deep and 10 mu m wide were formed in 60 min using additives in combination with pulse-reverse current and dissolved-oxygen enrichment. The effects of reverse current and dissolved oxygen on the performance of superfilling additives is discussed in terms of their effects on formation, destruction, and distribution of a Cu(I) thiolate accelerant. (c) 2005 The Electrochemical Society. All rights reserved.

High-performance vertical interconnection for high-density 3D chip stacking package

The three-dimensional (3D) chip stacking technology developed in ASET is a leading technology for realization of a high-density and high-performance system-in-package (SIP). As for the advanced interconnection technology, a 20-/spl mu/m-pitch low impedance vertical interconnection through Cu through via (TV) within thin chips plays the following roles: wide signal bus and very short electrical path for high-frequency signal transmission, strong power supplies and stable ground lines. The vertical interconnection was fabricated by inter chip connection (ICC) process, which includes Cu bump bonding (CBB) utilizing Cu-Sn diffusion for connecting Cu TVs without the formation of bumps on the chip back surface and encapsulation micro thin gap between chips. We elucidate the Cu-Sn diffusion phenomena and Cu oxide influence which were important CBB issues to realize the minute interconnection of Cu TVs. The temperature cycling test (TCT) was performed on chip on chip (COC) and 3D chip stacking structures fabricated by ICC process, and over 1,000 cycles reliability was confirmed. The consistent fabrication of vertical interconnection was realized. Then, we conducted the two important electrical evaluations. One is the DC resistance of the vertical interconnection, which measured only 15.4 m/spl Omega/ per layer. Another was the signal transmission delay, and only 0.9 ps was confirmed. Therefore, the vertical interconnection with Cu TV and ICC demonstrates the excellent capability of high performance interconnections on 3D chip stacking package. In addition, the micro scale strip line was evaluated to realize advanced SIP. The eye diagram on 3 Gbps indicated sufficient transmission. We will be able to realize high performance advanced SIP utilizing the vertical interconnection and high-speed horizontal line.

Two-Dimensional Electron Gas at GaAs/Ga0.52In0.48P Heterointerface Grown by Chloride Vapor-Phase Epitaxy

We report the first observation of two-dimensional electron gas at GaAs/Ga0.52In0.48P heterointerfaces using the Shub-nikov-de Haas measurements. The heterostructures were prepared by chloride vapor-phase epitaxy. The sheet carrier concentration is higher than that in GaAs/n-AlxGa1-xAs heterostructures with a similar donor-concentration in n-AlxGa1-xAs layers. This may be attributed to the facts that the dominant donors in the Ga0.52In0.48P layers are shallow and that the conduction-band discontinuity at the GaAs/Ga0.52In0.48P interfaces is large.

Semi‐insulator‐embedded InGaAsP/InP flat‐surface buried heterostructure laser

A new structure semi‐insulator‐embedded flat‐surface buried heterostructure 1.3 μm InGaAsP/InP laser has been developed using chloride vapor phase epitaxy. cw threshold currents as low as 18 mA and high‐temperature cw operation up to 100 °C have been obtained. Small‐signal response above 4 GHz has been achieved and no remarkable roll‐off has been observed, which is due to small parasitic capacitance.

Selective growth of InP buried structure by chloride vapor phase epitaxy

Selective growth of an InP buried layer by In/PCl3/H2 vapor phase epitaxy was developed for buried layer GaInAsP/InP long wavelength laser diodes. For the first time, a completely flat‐surface buried layer was grown into grooves with good morphology on a (100) exactly oriented InP substrate, but not on a (100) 2° off oriented substrate. We found that the side of the groove was covered with a buried InP layer in the early stage of epitaxial growth. Therefore, the present selective growth would be effective for the protection of the interface between the active and buried layers from thermal degradation. The resistivity of InP, measured by using an n‐i‐n structure, was found to be higher than 103 Ω cm at room temperature, which is sufficient for the buried layer of an usual laser diode.

Observation of Donor-Related Deep Levels in GaxIn1-xP (0.52≤x≤0.71)

This paper reports donor-related deep levels in GaxIn1-xP (0.52≤x≤0.71). S-, Se- and Si-doped GaInP grown by chloride-vapor-phase epitaxy were used for the measurements. At the Ga composition x of 0.52 that is lattice matched to GaAs, a deep level was observed for S-doped GaInP but not for Se- or Si-doped GaInP. Se-doped GaInP with larger x values was also studied, and the deep level was observed for x larger than 0.56. It is found that the behavior due to these donor-related deep levels, with effects such as persistent photoconductivity and Ga-composition dependence, is the same as for DX centers in AlGaAs.

Development of wafer thinning and double-sided bumping technologies for the three-dimensional stacked LSI

The three-dimensional (3D) chip stacking technology has been developed extensively recently for the next generation packaging technology. The technology includes thorough electrode fabrication, wafer thinning, wafer backside processing, testing, and chip stacking. Wafer thinning and wafer backside processing are important technologies among them, because these technologies accommodate small and thin form factor, enable thin chip stacking, and enhances electrical and mechanical reliability of the stacked module. In this paper, novel technologies of wafer thinning and wafer backside processes that include insulation film formation and bumping on the backside of the thinned wafer are described.

Donor-Related Deep Level in S-Doped Ga0.52In0.48P Grwon by Chloride VPE

A deep level in S-doped Ga0.52In0.48P grown on GaAs by chloride vapor-phase epitaxy was studied by deep-level transient spectroscopy (DLTS). The deep level concentration obtained by DLTS is increased with donor doping intensity as also the case for the obtained by persistent photoconductivity. The energy of this level strongly depends on thermal and optical ionization processes. These properties are the same as those of the DX center. However, the deep level concentration is considerably smaller than that in AlxGa1-xAs(0.3<x<0.7), which makes Ga0.52In0.48P favorable for heterostructure electron devices.

Two-dimensional-electron gas in undoped and selectively-doped GaInP/GaAs heterostructures grown by chloride-vapor-phase epitaxy

This paper reports characteristics of two-dimensional-electron gas (2DEG) in GaInP/GaAs heterostructures and their availability to electronic devices. The heterostructures were fabricated by chloride-vapor-phase epitaxy. The band discontinuity was estimated using an empirical rule. A low-temperature mobility of 2DEG greater than 100,000 cm2/Vs was obtained for the undoped structure. 2DEG was also observed in S or Se selectively-doped structures without incorporating the undoped-spacer layer. Apparent temperature dependence and photoresponse of 2DEG were interpreted with the models which have been used for GaInAs/InP heterostructures.

Surface Morphology and Line Fill Properties of Gold Grown by Organometallic Chemical Vapor Deposition

Dimethyl gold hexafluoroacetylacetonate, (DMAu(hfac)) was used to grow gold films by thermal decomposition. We found that surface morphology and line fill properties greatly depend on the substrate temperature and reactor pressure. Under optimum growth conditions, we have obtained gold films with flat surfaces and fine line fillings. We propose a growth model to explain the variation in surface morphology at various growth temperatures and reactor pressures.